Abstract: A monitoring device on-chip. The monitoring device includes characteristic circuits, test circuits, and select circuits and is incorporated into an integrated circuit. The test circuit is cascaded by the characteristic circuit and a select circuit is incorporated to switch to output the test signal or the characteristic signal. There is another select circuit to switch the output signal of the integrated circuit in a normal mode or the signal of the output end of the characteristic circuit. Therefore, the output end of the select circuit can output the integrated circuit's signals, test signals, and characteristic signals without additional output pins.

Abstract: A monitor device on-chip. The monitor device including characteristic circuits, test circuits, and select circuits is incorporated into an integrated circuit. The test circuit is cascaded by the characteristic circuit and a select circuit is incorporated to switch to output the test signal or the characteristic signal. There is an another select circuit to switch the output signal of the integrated circuit in normal mode or the signal of the output end of the characteristic circuit. Therefore, the output end of the select circuit can output integrated circuit's signals, test signals, and characteristic signals without additional output pins.

Abstract: An inspection apparatus and method for test mode circuit and test ambient on an integrated circuit chip. The integrated circuit chip has an input pin, an output pin and a function circuit. The inspection apparatus has a test mode circuit and a test pattern generator. The test mode circuit is built in the integrated circuit chip to test the function circuit. The test pattern generator is coupled to the input pin to receive a test signal. According to the operation of the test mode circuit, an output signal is output from the output pin. According to the output signal, whether the test mode circuit and the test ambient are correct is determined. Thus, when problems occur while testing chips, a lot of time of analysis is saved. Whether the problems occur from the function circuit, the test mode circuit or the test ambient set up is realized.

Abstract: An architecture for wafer scale memories and a placement method replaces defective chips with spare chips in a memory module so as to provide minimum critical signal delay. The SDRAM memory chips are classified into normal chips and spare chips, where the normal chips are formed into groups such as rows or columns, and the spare chips are used to replace defective normal chips. A delay model for metal lines and vias is used to compute the signal delay for placement and routing. The placement problem is modeled as a bipartite graph and solved using a branch and bound algorithm to obtain a chip replacement configuration having the shortest critical signal delay. Also described is a hierarchical routing approach, which classifies the signals into different types and levels of signals.

Abstract: A power source design for embedded memory uses independent power sources such that a first power source group is linked to the DRAM, a second power source group is linked to the logic unit and a third power source group is linked to the testing mode circuit with input/output ports during the silicon chip stage. In the packaging stage the first power source group, the second power source group and the third power source group are joined together. The design is able to prevent testing errors or instability due to direct current from floating nodes in the silicon chip testing stage, and prevent a potential latch-up problem in the packaging stage.

Abstract: A test pattern generator accompanying digital integrated circuits for successively generating a plurality of test patterns for a built-in self test. A plurality of shift registers are serially connected in a loop for successively outputting the test patterns in response to a clock signal. At least one logic gate is connected among the shift registers. At least one control means is connected within the loop. Using such a configuration, the shift registers are set to an initial pattern. The shift registers are then set to one of a plurality of test patterns. The test patterns are then successively output through the shift registers in response to the clock signal.