Patents by Inventor Cheng-Ju Wu
Cheng-Ju Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240420994Abstract: A semiconductor device includes a substrate, a heat dissipation dielectric layer, a conductive interconnect structure, and a blocking dielectric layer. The heat dissipation dielectric layer is disposed on the substrate and has a thermal conductivity greater than 10 W/mK. The conductive interconnect structure is disposed in the heat dissipation dielectric layer. The blocking dielectric layer is disposed in the heat dissipation dielectric layer to isolate the conductive interconnect structure from the heat dissipation dielectric layer.Type: ApplicationFiled: June 14, 2023Publication date: December 19, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Ling SU, Ming-Hsien LIN, Hsin-Ping CHEN, Shao-Kuan LEE, Cheng-Chin LEE, Yen-Ju WU, Hsin-Yen HUANG, Hsi-Wen TIEN, Chih-Wei LU, Chia-Chen LEE
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Publication number: 20240413074Abstract: A method for forming a semiconductor device structure is disclosed. The method includes forming one or more first conductive features in a first dielectric layer, forming a metal layer on each of the one or more first conductive features, forming a first etch stop layer over the metal layer, forming a second etch stop layer on the first etch stop layer, wherein the second etch stop layer is a nitrogen-free layer. The method also includes forming a second dielectric layer on the second etch stop layer, and forming a second conductive feature in the second dielectric layer through the second etch stop layer, the first etch stop layer, and the metal layer.Type: ApplicationFiled: June 9, 2023Publication date: December 12, 2024Inventors: Cheng-Chin Lee, Hsin-Yen Huang, Yen Ju Wu, Shao-Kuan Lee, Kuang-Wei Yang, Hsiao-Kang Chang
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Publication number: 20240413010Abstract: A method of forming a semiconductor structure is provided. A first dielectric layer is formed over a substrate. A first metal pattern is formed through the first dielectric layer. A metal cap is formed over the first metal pattern. A surface portion of the metal cap is silicided to form a metal silicide pattern. A composite etch stop layer is formed on the first dielectric layer and the metal silicide pattern. A second dielectric layer is formed on the composite etch stop structure. A second metal pattern is formed through the second dielectric layer and the composite etch stop structure and landed on the metal silicide pattern.Type: ApplicationFiled: June 8, 2023Publication date: December 12, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen Ju Wu, Chi-Lin Teng, Cheng-Chin Lee, Shao-Kuan Lee, Kai-Fang Cheng, Hsin-Yen Huang, Hsiao-Kang Chang
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Publication number: 20240413075Abstract: A semiconductor structure includes a base structure including a substrate and a device unit disposed on a front surface of the substrate, a front dielectric portion disposed on the front surface to cover the device unit, a front conductive layer disposed in the front dielectric portion and connected to the device unit, a back dielectric unit disposed on a back surface of the substrate opposite to the front surface and including at least one first part which includes a first dielectric portion having a thermal conductivity which is greater than that of the front dielectric portion, and a back conductive unit which is disposed in the back dielectric unit and connected to the device unit, and which includes at least one first conductive layer disposed in the at least one first part.Type: ApplicationFiled: June 12, 2023Publication date: December 12, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Chin LEE, Hsin-Yen HUANG, Hsiao-Kang CHANG, Yen-Ju WU, Shao-Kuan LEE, Li-Ling SU, Chia-Chen LEE
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Patent number: 12165920Abstract: A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.Type: GrantFiled: August 30, 2021Date of Patent: December 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hwei-Jay Chu, Chieh-Han Wu, Cheng-Hsiung Tsai, Chung-Ju Lee
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Publication number: 20240379437Abstract: A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.Type: ApplicationFiled: July 25, 2024Publication date: November 14, 2024Inventors: HWEI-JAY CHU, CHIEH-HAN WU, CHENG-HSIUNG TSAI, CHUNG-JU LEE
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Publication number: 20240339396Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.Type: ApplicationFiled: June 17, 2024Publication date: October 10, 2024Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
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Patent number: 12051659Abstract: Semiconductor devices are provided. The semiconductor device includes a substrate, an interconnect structure, and a conductive pad structure. The interconnect structure is over the substrate and includes a top metal layer. The conductive pad structure is over the interconnect structure and includes a lower barrier film, an upper barrier film, and an aluminum-containing layer. The lower barrier film is on the top metal layer. The upper barrier film is on the lower barrier film and has an amorphous structure. The aluminum-containing layer is on the upper barrier film. The lower barrier film and the upper barrier film are made of a same material, and a nitrogen atomic percentage of the upper barrier film is higher than a nitrogen atomic percentage of the lower barrier film.Type: GrantFiled: May 10, 2023Date of Patent: July 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hsun Huang, Po-Han Wang, Ing-Ju Lee, Chao-Lung Chen, Cheng-Ming Wu
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Publication number: 20240249494Abstract: An environment managing and monitoring system and a method using same are provided. The environment managing and monitoring system is configured to assist monitors to obtain real-time information of the monitoring field and control device in the monitoring field. The environmental managing and monitoring system includes at least one sub-system and a host system. The host system is configured to output a region of interest condition and a monitoring condition to the sub-system, wherein the sub-system is configured to generate monitoring results according to the monitoring conditions, and selects an image range from the captured wide-angle dynamic real-time images according to the region of interest condition.Type: ApplicationFiled: September 4, 2023Publication date: July 25, 2024Inventors: Yung-tai SU, Hsin-lung HSIEH, Yu-hsuan LIAO, Yu-min CHUANG, Pang-tzu LIU, Chun-yueh CHEN, Jia-hao LU, Cheng-ju HSUIEH, Ching-wei LEE, Tsung-hsun TSAI, Po-yuan KUO, Po-yi WU, Chen-wei CHOU
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Patent number: 12046551Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.Type: GrantFiled: April 17, 2023Date of Patent: July 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
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Publication number: 20240000649Abstract: A patient brace system and method of using the same are disclosed for treatment of lower extremity injuries. Described brace systems include a crutch, at least one crutch sensor, a patient brace, at least one controller, and a rehabilitation application. The crutch sensor(s) measure one or more crutch parameters. The controller(s) are operable to receive and process a signal(s) indicative of the crutch parameter(s) and produces patient gait data that, in turn, is communicated to a data hub. In some embodiments, the patient brace may also include at least one brace sensor configured to similarly communicate with the data hub. The rehabilitation application is communication with the data hub and determines a response output based on the information fed to the data hub, the application then communicating the response output to at least one of a caregiver, a user of the patient brace, and/or to the patient brace.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: David B. Spenciner, Cheng-Ju Wu, Drew Miller, Steven Nguyen, Ravi Patel
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Publication number: 20230062659Abstract: A blood pressure lowering training device comprises a head frame unit corresponding to a user's head shape, an audio stimulation unit for broadcasting binaural beats with frequency following response to both ears of the user, a display unit including a display module for displaying a virtual image and blood pressure information and a blood pressure measurement module for measuring blood pressure, and a control unit electrically connected with the audio stimulation unit and the display unit, so that the hypertensive patient can perform a variety of adjustable blood pressure lowering training in one use process, and effectively improve the use intention of the hypertensive patient.Type: ApplicationFiled: August 26, 2022Publication date: March 2, 2023Inventors: Chen-Chao HSU, Shin-Da LEE, Yi-Yuan LIN, Cheng-Ju WU
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Publication number: 20230066923Abstract: A wearable brain multi-stimulation pain control device is provided, comprising a main support unit, an auxiliary support unit, an audio stimulation unit, and an optical frequency-flashed stimulation unit. The main support unit includes two ear portions corresponding to a user’s ears and a front side portion, and the auxiliary support unit includes a mounting portion. Two opposite ends of the mounting portion are pivoted to the main support unit, and the audio stimulation unit includes two speakers that are respectively arranged on the ear portions and can broadcast a binaural beats with frequency following response. The optical frequency-flashed stimulation unit is arranged on the front side portion and can stimulate at least one eye of the user with flickering light, so that the user can obtain multiple stimulations at the same time in a single course of treatment to achieve the effect of improving pain.Type: ApplicationFiled: August 26, 2022Publication date: March 2, 2023Inventors: Chen-Chao HSU, Shin-Da LEE, Cheng-Ju WU
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Patent number: 11364170Abstract: A joint mobilization apparatus includes a pulling unit and a power unit. The pulling unit includes a wearable member set for mounting on the patient's joint part, and a rope set connected to the wearable member set. The power unit provides power of reciprocatingly pulling the rope set, and includes a shell member, a motor, and a reciprocation mechanism connected to the motor and the rope set. The reciprocation mechanism is driven by the motor to reciprocate relative to the shell member, so as to pull the rope set to reciprocate the wearable member set and patient's joint part. By using the power unit to drive the pulling unit to pull reciprocatingly for mobilizing the patient's joint part, instead of the therapist's treatment, the therapist's burden in physical strength can be reduced. Furthermore, the joint mobilization apparatus can provide the user to execute various muscle training modes.Type: GrantFiled: November 28, 2019Date of Patent: June 21, 2022Assignee: Asia UniversityInventors: Shin-Da Lee, Cheng-Ju Wu, Wei-Chun Hsu, Hong-Jun Yeh
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Publication number: 20200170872Abstract: A joint mobilization apparatus includes a pulling unit and a power unit. The pulling unit includes a wearable member set for mounting on the patient's joint part, and a rope set connected to the wearable member set. The power unit provides power of reciprocatingly pulling the rope set, and includes a shell member, a motor, and a reciprocation mechanism connected to the motor and the rope set. The reciprocation mechanism is driven by the motor to reciprocate relative to the shell member, so as to pull the rope set to reciprocate the wearable member set and patient's joint part. By using the power unit to drive the pulling unit to pull reciprocatingly for mobilizing the patient's joint part, instead of the therapist's treatment, the therapist's burden in physical strength can be reduced. Furthermore, the joint mobilization apparatus can provide the user to execute various muscle training modes.Type: ApplicationFiled: November 28, 2019Publication date: June 4, 2020Applicant: Asia UniversityInventors: Shin-Da Lee, CHENG-JU WU, WEI-CHUN HSU, HONG-JUN YEH
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Patent number: 10522974Abstract: An edge-emitting laser having a small vertical emitting angle includes an upper cladding layer, a lower cladding layer and an active region layer sandwiched between the upper and lower cladding layers. By embedding a passive waveguide layer within the lower cladding to layer, an extended lower cladding layer is formed between the passive waveguide layer and the active region layer. In addition, the refractive index (referred as n-value) of the passive waveguide layer is larger than the n-value of the extended lower cladding layer. The passive waveguide layer with a larger n-value would guide the light field to extend downward. The extended lower cladding layer can separate the passive waveguide layer and the active region layer and thus expand the near-field distribution of laser light field in the resonant cavity, so as to obtain a smaller vertical emitting angle in the far-field laser light field.Type: GrantFiled: May 31, 2018Date of Patent: December 31, 2019Assignee: TrueLight CorporationInventors: Chien Hung Pan, Cheng-Ju Wu
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Publication number: 20180366908Abstract: An edge-emitting laser having a small vertical emitting angle includes an upper cladding layer, a lower cladding layer and an active region layer sandwiched between the upper and lower cladding layers. By embedding a passive waveguide layer within the lower cladding to layer, an extended lower cladding layer is formed between the passive waveguide layer and the active region layer. In addition, the refractive index (referred as n-value) of the passive waveguide layer is larger than the n-value of the extended lower cladding layer. The passive waveguide layer with a larger n-value would guide the light field to extend downward. The extended lower cladding layer can separate the passive waveguide layer and the active region layer and thus expand the near-field distribution of laser light field in the resonant cavity, so as to obtain a smaller vertical emitting angle in the far-field laser light field.Type: ApplicationFiled: May 31, 2018Publication date: December 20, 2018Applicant: TRUELIGHT CORPORATIONInventors: Chien Hung Pan, Cheng-Ju Wu
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Patent number: 10014663Abstract: An edge-emitting laser having a small vertical emitting angle includes an upper cladding layer, a lower cladding layer and an active region layer sandwiched between the upper and lower cladding layers. By embedding a passive waveguide layer within the lower cladding layer, an extended lower cladding layer is formed between the passive waveguide layer and the active region layer. In addition, the refractive index (referred as n-value) of the passive waveguide layer is larger than the n-value of the extended lower cladding layer. The passive waveguide layer with a larger n-value would guide the light field to extend downward. The extended lower cladding layer can separate the passive waveguide layer and the active region layer and thus expand the near-field distribution of laser light field in the resonant cavity, so as to obtain a smaller vertical emitting angle in the far-field laser light field.Type: GrantFiled: June 16, 2017Date of Patent: July 3, 2018Assignee: TrueLight CorporationInventors: Chien Hung Pan, Cheng-Ju Wu
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Patent number: 9165746Abstract: An electron beam drift detection device and a method for detecting electron beam drift are provided in which the method includes placing a predetermined characteristic identification pattern on a surface of a workpiece; emitting an electron beam, and focusing and deflecting the electron beam such that the focused and deflected electron beam scans the surface of the workpiece and the characteristic identification pattern; detecting backscattered electrons and secondary electrons; and receiving detection signals and performing an image process on the detection signals to obtain an electronic image of the characteristic identification pattern, and measuring a drift degree by comparing the electronic image with the predetermined shape of the characteristic identification pattern.Type: GrantFiled: September 23, 2011Date of Patent: October 20, 2015Assignee: National Taiwan UniversityInventors: Jia-Yush Yen, Yung-Yaw Chen, Yi-Hung Kuo, Cheng-Ju Wu
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Patent number: 8786073Abstract: A packaging device for matrix-arrayed semiconductor light-emitting elements of high power and high directivity comprises a metal base, an array chip and a plurality of metal wires. The metal base is of highly heat conductive copper or aluminum, and a first electrode area and at least one second electrode area which are electrically isolated are disposed on the metal base. The array chip is disposed on the first electrode area, on which multiple matrix-arranged semiconductor light-emitting elements and at least one wire bond pad adjacent to the light-emitting elements are disposed. The light-emitting element is a VCSEL element, an HCSEL element or an RCLED element. The metal wires are connected between the wire bond pad and the second electrode area to transmit power signals. Between the bottom surface and the first electrode area is disposed a conductive adhesive to bond and facilitate electrical connection between the two.Type: GrantFiled: October 23, 2012Date of Patent: July 22, 2014Assignee: TrueLight CorporationInventors: Cheng Ju Wu, Hung-Che Chen, I Han Wu, Shang-Cheng Liu, Jin Shan Pan