Abstract: A DC level redistribution method includes the steps of: receiving all positive signals and one negative signal of a plurality of pairs of differential signals; fixing a DC level of a positive signal of a designated pair of differential signals among a plurality of pairs of differential signals as a reference in order to adjust a DC level of a negative signal of the designated pair of differential signals for generating an adjusted negative signal; and taking the adjusted negative signal of the designated pair of differential signals as a reference in order to adjust DC levels of the positive signals of the other pairs of differential signals excluding the designated pair of differential signals. The DC redistribution method may be used in a display system.

Abstract: An electrostatic discharge (ESD) protection circuit is disclosed, which comprises an ESD detection circuit and protection switches. If an ESD event occurs, the ESD detection circuit turns off the protection switches so as to protect an application circuit provided in integrated circuits (IC) from being damaged by the electrostatic discharge, and if not, the ESD detection circuit turns on the protection switches so as to make the application circuit provided in integrated circuits (IC) function normally.

Abstract: An analog front-end processing apparatus capable of sharing pins includes a plurality of positive pins, a negative pin, a plurality of positive clamping circuits, a negative clamping circuit, a plurality of sample and hold circuits and a plurality of adjusting circuits. The positive clamping circuits have positive signals fixed at their corresponding target positive voltages. The negative clamping circuit has a negative signal fixed at a first reference voltage. Each sample and hold circuit has a positive input terminal and a negative input terminal, wherein a voltage difference between the two input terminals is substantially equal to a voltage difference between the corresponding target positive voltage and the first reference voltage during a sample period, and a voltage difference between the two input terminals is equal to a voltage difference between the corresponding target negative voltage and a second reference voltage during a hold period.

Abstract: A DC level redistribution method includes the steps of: receiving all positive signals and one negative signal of a plurality of pairs of differential signals; fixing a DC level of a positive signal of a designated pair of differential signals among a plurality of pairs of differential signals as a reference in order to adjust a DC level of a negative signal of the designated pair of differential signals for generating an adjusted negative signal; and taking the adjusted negative signal of the designated pair of differential signals as a reference in order to adjust DC levels of the positive signals of the other pairs of differential signals excluding the designated pair of differential signals. The DC redistribution method may be used in a display system.

Abstract: An analog front-end processing apparatus capable of sharing pins includes a plurality of positive pins, a negative pin, a plurality of positive clamping circuits, a negative clamping circuit, a plurality of sample and hold circuits and a plurality of adjusting circuits. The positive clamping circuits have positive signals fixed at their corresponding target positive voltages. The negative clamping circuit has a negative signal fixed at a first reference voltage. Each sample and hold circuit has a positive input terminal and a negative input terminal, wherein a voltage difference between the two input terminals is substantially equal to a voltage difference between the corresponding target positive voltage and the first reference voltage during a sample period, and a voltage difference between the two input terminals is equal to a voltage difference between the corresponding target negative voltage and a second reference voltage during a hold period.

Abstract: An electrostatic discharge (ESD) protection circuit is disclosed, which comprises an ESD detection circuit and protection switches. If an ESD event occurs, the ESD detection circuit turns off the protection switches so as to protect an application circuit provided in integrated circuits (IC) from being damaged by the electrostatic discharge, and if not, the ESD detection circuit turns on the protection switches so as to make the application circuit provided in integrated circuits (IC) function normally.

Abstract: The present invention provides a circuit that utilizes OP-sharing technique. The circuit includes an amplifier, a first application circuit, a second application circuit, and a reset circuit. The first application circuit drives the amplifier during at least a first working period. The second application circuit drives the amplifier during at least a second working period. The reset circuit resets the amplifier during at least a third working period. The third working period is between the first working period and the second working period.

Abstract: A pipeline analog-to-digital converter including: a first conversion module, a second conversion module, at least a comparator, a first switch module and a second switch module. The first conversion module includes a first storage unit and a first multiplying digital-to-analog converter (MDAC). An input end of the second conversion module is coupled in series with an output end of the first conversion module. The second conversion module includes a second storage unit and a second MDAC. The first switch module is utilized for coupling the input end of the first conversion module or the second conversion module to an input end of the comparator; and the second switch module is utilized for coupling an output end of the comparator to the first or the second storage unit.

Abstract: The present invention provides a circuit that utilizes OP-sharing technique. The circuit includes an amplifier, a first application circuit, a second application circuit, and a reset circuit. The first application circuit drives the amplifier during at least a first working period. The second application circuit drives the amplifier during at least a second working period. The reset circuit resets the amplifier during at least a third working period. The third working period is between the first working period and the second working period.

Abstract: A pipeline analog-to-digital converter including: a first conversion module, a second conversion module, at least a comparator, a first switch module and a second switch module. The first conversion module includes a first storage unit and a first multiplying digital-to-analog converter (MDAC). An input end of the second conversion module is coupled in series with an output end of the first conversion module. The second conversion module includes a second storage unit and a second MDAC. The first switch module is utilized for coupling the input end of the first conversion module or the second conversion module to an input end of the comparator; and the second switch module is utilized for coupling an output end of the comparator to the first or the second storage unit.