Abstract: Various embodiments of a 3DIC die package, including trench capacitors integrated with IC dies, are disclosed. A 3DIC die package includes a first IC die and a second IC die disposed on the first IC die. The first IC die includes a substrate having a first surface and a second surface opposite to the first surface, a first active device disposed on the first surface of the substrate, and a passive device disposed on the second surface of the substrate. The passive device includes a plurality of trenches disposed in the substrate and through the second surface of the substrate, first and second conductive layers disposed in the plurality of trenches and on the second surface of the substrate, and a first dielectric layer disposed between the first and second conductive layers. The second IC die includes a second active device.

Abstract: A semiconductor package structure includes a first redistribution layer, a first semiconductor die, a second through via, a molding material, a second semiconductor die, and a second redistribution layer. The first semiconductor die is disposed over the first redistribution layer and includes a first through via having a first width. The second through via is adjacent to the first semiconductor die and has a second width. The second width is greater than the first width. The molding material surrounds the first semiconductor die and the second through via. The second semiconductor die is disposed over the molding material and is electrically coupled to the first through via and the second through via. The second redistribution layer is disposed over the second semiconductor die.

Abstract: A semiconductor structure includes a base layer, semiconductor dies on the base layer, and an inter-die connection layer electrically connecting two adjacent semiconductor dies. Each of the semiconductor dies includes an active area and a seal ring area including a seal ring surrounding the active area. The inter-die connection layer extends over adjacent portions of the seal rings in the seal ring areas of the two adjacent semiconductor dies.

Abstract: An integrated circuit includes a substrate and a plurality of standard cells. The standard cells are formed on the substrate, wherein each standard cell comprises a first fin, a second fin and a third fin, the second fin is located between the first fin and the third fin, and there is a first interval between the first fin and the second fin is different from a second interval between the first fin and the third fin.

Abstract: An integrated circuit includes a substrate and a plurality of standard cells. The standard cells are formed on the substrate, wherein each standard cell comprises a first fin, a second fin and a third fin, the second fin is located between the first fin and the third fin, and there is a first interval between the first fin and the second fin is different from a second interval between the first fin and the third fin.

Abstract: The invention provides an integrated circuit transformer disposed on a substrate. The integrated circuit transformer includes a first coiled metal pattern disposed on the substrate, comprising an inner loop segment and an outer loop segment. A second coiled metal pattern is disposed on the substrate, laterally between the inner loop segment and the outer loop segment. A dielectric layer is disposed on the first coiled metal pattern and the second coiled metal pattern. A first via is formed through the dielectric layer, electrically connecting to one of the first and second coiled metal patterns. A first redistribution pattern is disposed on the dielectric layer, electrically connecting to and extending along the first via, wherein the first redistribution pattern covers at least a portion of the first coiled metal pattern and at least a portion of the second coiled metal pattern.

Abstract: The invention provides an integrated circuit transformer disposed on a substrate. The integrated circuit transformer includes a first coiled metal pattern disposed on the substrate, comprising an inner loop segment and an outer loop segment. A second coiled metal pattern is disposed on the substrate, laterally between the inner loop segment and the outer loop segment. A dielectric layer is disposed on the first coiled metal pattern and the second coiled metal pattern. A first via is formed through the dielectric layer, electrically connecting to one of the first and second coiled metal patterns. A first redistribution pattern is disposed on the dielectric layer, electrically connecting to and extending along the first via, wherein the first redistribution pattern covers at least a portion of the first coiled metal pattern and at least a portion of the second coiled metal pattern.

Abstract: A method for forming the self-aligned buried N+-type to diffusion process in ETOX flash cell is disclosed. The method at least includes the following steps. First of all, a substrate is provided having a pad oxide layer thereon, a dielectric layer on the pad oxide layer, and a cap layer on the dielectric layer. Then, a portion of the cap layer and the dielectric layer are etched to stop on the pad oxide layer to define an active region. Then, a spacer is formed on sidewall of the dielectric layer. Next, a portion of the pad oxide layer and the substrate are etched through said buried N+-type region to form an opening in the substrate. Finally, a field oxide region is formed in the substrate.

Abstract: A method for forming the self-aligned buried N+-type to diffusion process in ETOX flash cell is disclosed. The method at least includes the following steps. First of all, a substrate is provided having a pad oxide layer thereon, a dielectric layer on the pad oxide layer, and a cap layer on the dielectric layer. Then, a portion of the cap layer and the dielectric layer are etched to stop on the pad oxide layer to define an active region. Then, a spacer is formed on sidewall of the dielectric layer. Next, a portion of the pad oxide layer and the substrate are etched through said buried N+-type region to form an opening in the substrate. Finally, a field oxide region is formed in the substrate.