Abstract: A mesoporous cerium oxide nano-material and a preparation method and an application thereof are provided in the present disclosure, belonging to the technical field of porous materials. The preparation method includes the following steps: using porous organic frameworks material as a templating agent, impregnating and adsorbing cerium salt precursor under an action of alkali, and removing the templating agent by roasting pyrolysis to obtain the mesoporous cerium oxide nano-material. POFs is carbonized into mesoporous carbon materials by calcination in inert atmosphere, which supports the mesoporous channels of cerium oxide, and then the carbonized carbon materials of POFs are removed by calcination in air atmosphere, forming the mesoporous structure of cerium oxide. The mesoporous cerium oxide nano-material prepared by the present disclosure has a high specific surface area and mesoporous structure, and is used as a catalytic material or catalyst carrier.

Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes: providing an interposer having a front surface and a back surface, the interposer comprising a substrate, at least one routing region, and at least one non-routing region; forming at least one warpage-reducing trench in the at least one non-routing region, wherein the at least one warpage-reducing trench extends from the front surface of the interposer to a first depth, the first depth smaller than a thickness between the front surface and the back surface of the interposer; depositing a warpage-relief material in the at least one warpage-reducing trench; and bonding the group of IC dies to the front surface of the interposer.

Abstract: Apparatus and methods for handling semiconductor part carriers are disclosed. In one example, an apparatus for handling semiconductor part carriers is disclosed. The apparatus includes a mechanical arm and an imaging system coupled to the mechanical arm. The mechanical arm is configured for holding a semiconductor part carrier. The imaging system is configured for automatically locating a goal position on a surface onto which the semiconductor part carrier is to be placed.

Abstract: A method of manufacturing a semiconductor device includes forming M_1st segments in a first metallization layer including: forming first and second M_1st segments for which corresponding long axes extend in a first direction and are substantially collinear, the first and second M_1st segments being free from another instance of M_1st segment being between the first and second M_1st segments; and (A) where the first and second M_1st segments are designated for corresponding voltage values having a difference equal to or less than a reference value, separating the first and second M_1st segments by a first gap; or (B) where the first and second M_1st segments are designated for corresponding voltage values having a difference greater than the reference value, separating the first and second M_1st segments by a second gap, a second size of the second gap being greater than a first size of the first gap.

Abstract: The present disclosure provides a preparation method of a mesoporous CeO2-loaded Au catalyst, products and applications thereof, and belongs to the technical field of fine organic chemical industry. According to the present disclosure, firstly, COFs material COFs-41 is employed to prepare mesoporous CeO2 carrier material with high specific surface area; then, Au nanoparticles loaded on the surface of mesoporous CeO2 carrier pores are anchored by impregnation-reduction method to produce Au@CeO2 catalyst with high specific surface area; and then, mesoporous Au@CeO2 catalyst with high specific surface area, aromatic alcohols are added to a reactor, anhydrous methanol is used as a solvent, and heating is carried out to react in an atmosphere of atmospheric oxygen for a certain period of time at room temperature, and this catalyst catalyzes the oxidative transesterification of aromatic alcohols for synthesis of aromatic esters in a highly selective manner.

Abstract: A method includes forming a metal layer over a dielectric layer; forming hard masks over the metal layer; etching the metal layer using the hard masks as etch mask to form metal features; selectively forming dielectric liners on opposite sidewalls of each of the metal features, while leaving surfaces of the hard masks and the dielectric layer exposed by the dielectric liners; and forming an inter-metal dielectric layer laterally surrounding the metal features.

Abstract: A semiconductor device package, along with methods of forming such, are described. The semiconductor device package includes a first semiconductor device structure having a first substrate, two first devices disposed on the first substrate, a first interconnection structure disposed over the first substrate and the two first devices, and a first thermal feature disposed through the first substrate and the first interconnection structure. The semiconductor device package further includes a second semiconductor device structure disposed over the first semiconductor device structure having a second interconnection structure disposed over the first interconnection structure, a second substrate disposed over the second interconnection structure, two second devices disposed between the second substrate and the second interconnection structure, and a second thermal feature disposed through the second substrate and the second interconnection structure.

Abstract: A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.

Abstract: The present application relates to a striker assembly and a seat assembly. A striker assembly includes a motor, a worm screw operably coupled with the motor, a gear segment engaged with the worm screw, and a striker connected to the gear segment and configured for engagement with a latch of a seat back of the seat to adjustably couple the seat back with a mounting surface.

Abstract: A system for monitoring and controlling an EUV light source includes a first temperature sensor, a signal processor, and a process controller. The first temperature sensor includes a portion inserted into a space surrounded by a plurality of vanes through a vane of the plurality of vanes, and obtains an ambient temperature that decreases with time as a function of tin contamination coating on the inserted portion. The signal processor determines an excess tin debris deposition on the vane based on the obtained chamber ambient temperature. The process controller activates a vane cleaning action upon being informed of the excess tin debris deposition by the signal processor, thereby improving availability of the EUV light source tool and reducing risks of tin pollution on other tools such as a reticle.

Abstract: The disclosure discloses a data writing operation method and device of a resistive random access memory, and the method includes: applying a first pulse voltage to the resistive random access memory, and adding one to a corresponding number to obtain a first number; if the current first number is greater than a first set upper limit value and a current second number is smaller than or equal to a second set upper limit value, obtaining a test value; if the test value does not satisfy a preset condition, applying a second pulse voltage to the resistive random access memory, and adding one to the corresponding number to obtain a second number until the test value satisfies the preset condition or the current second number is greater than the second set upper limit value, thereby improving the writing efficiency.

Abstract: Pixels in an organic light-emitting diode (OLED) display may be microcavity OLED pixels having optical cavities. The optical cavities may be defined by a partially transparent cathode layer and a reflective anode structure. The anode of the pixels may include both the reflective anode structure and a supplemental anode that is transparent and that is used to tune the thickness of the optical cavity for each pixel. Organic light-emitting diode layers may be formed over the pixels and may have a uniform thickness in each pixel in the display. Pixels may have a conductive spacer between a transparent anode portion and a reflective anode portion, without an intervening dielectric layer. The conductive spacer may be formed from a material such as titanium nitride that is compatible with both anode portions. The transparent anode portions may have varying thicknesses to control the thickness of the optical cavities of the pixels.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.

Abstract: A method is provided. The method includes the following steps: identifying a first intellectual property (IP) block and a second IP block in an integrated circuit; identifying a small border region between the first IP block and the second IP block, wherein the small border region has a width in a first horizontal direction, and the width is between a small border region dimension lower limit and a small border region dimension upper limit; and inserting at least one small dummy gate feature pattern in the small border region.

Abstract: A system and method for a content-centric personalized recommendation engine that includes processing user data comprised of user feature data as input to a user neural network model and yielding a user embedding; processing the user embedding through a matchmaking neural network, which is a trained model to map user embeddings and content embeddings to a shared dimensional space, and yielding a user shared-item embedding; and applying analysis of the user shared-item embedding in selecting at least one content item associated with a content shared-item embedding within the matchmaking neural network.

Abstract: The present disclosure discloses a management system, including a beacon tag device, a docking station device, and a backend server. The beacon tag device includes a wireless communication chip and a processor. The wireless communication chip is configured to send a beacon signal. The docking station device includes an interface, a sensor, a wireless sensor network transceiver circuit, a wireless network transceiver circuit, and a control circuit. The backend server is communicatively connected to the docking station device. When the sensor receives the beacon signal, the control circuit determines whether the RSSI of the beacon signal is greater than a beacon strength threshold. If yes, the docking station device sends a sign-in/sign-out signal to the backend server.

Abstract: The present invention discloses a vascular bone organoid and its compression-perfusion fabricator system. The compression-perfusion fabricator system includes a compression device, a perfusion chamber, a perfusion device, and a microcomputer driver. The compression device and the perfusion device are controlled and adjusted through the microcomputer driver to simultaneously provide dynamic mechanical compression and perfusion stimulation. The system simulates the dynamic microenvironment within the human body. The present invention further utilizes 3D bioprinting technology to manufacture a vascular bone organoid, which is cultured in the compression-perfusion fabricator system, to mimic the growth of bone and vascular endothelial cells within the normal dynamic physiological environment of the bone marrow cavity.

Abstract: An apparatus for handling semiconductor part carriers includes: a mechanical arm and an imaging system coupled to the mechanical arm, wherein the mechanical arm is configured for holding a semiconductor part carrier, and the imaging system is configured for automatically locating a goal position on a surface onto which the semiconductor part carrier is to be placed.

Abstract: A package comprises an interposer, comprising an interposer substrate including at least one layer, and a plurality of RDLs formed through at least a portion of the interposer substrate. The package also includes a die device structure comprising at least one device die, and a first test line (TL) structure interposed between the interposer and the die device structure. The first TL structure includes at least one first test line electrically coupled to the at least one device die, at least a portion of the at least one first test line extending beyond a peripheral edge of the die device structure to provide an electrical interface with the at least one device die.

Abstract: In an embodiment a system includes: an automated vehicle configured to traverse a first predetermined path; and a sensor system located on the automated vehicle, the sensor system configured to detect a vertical obstacle along the first predetermined path along one or two floorboards ahead of the automated vehicle, wherein the automated vehicle is configured to traverse a second predetermined path in response to detecting the vertical obstacle.