Patents by Inventor Cheng-Kang Wang

Cheng-Kang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8572452
    Abstract: A block code decoding method and device thereof are provided. The procedure of the bounded distance decoding is simplified and the number of correlation calculating is reduced via a set of pre-established XOR masks. The decoding method includes: picking up the source code part of the received message; executing a XOR calculating for the source code part with the XOR masks, and encoding the results thereof to produce a set of compared codes; executing a correlation calculating for the set of compared codes and the received message; and determining a compared code having the maximum correlation result as the decision.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: October 29, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventors: Cheng-Kang Wang, Chun-Ming Cho, Chia Chun Hung
  • Patent number: 8527857
    Abstract: A parity-check-code decoder is adapted for receiving a channel quality ratio and at least (N) bits that are to be decoded. The parity-check-code decoder treats each of the bits as a bit node, and includes: a verifying circuit that multiplies (N) bit nodes by a matrix to obtain (N-K) check nodes; a reliability-generating circuit that generates a reliability index that serves as an extrinsic check index for each of the bit nodes to transmit to the check nodes; a bit exchange circuit that generates an extrinsic bit index for each of the check nodes to transmit to the bit nodes; a check-exchange circuit that updates a plurality of the extrinsic check indices based on the extrinsic bit indices for the bit nodes to transmit to the check nodes; and a reliability-updating circuit that updates the reliability index of and determines an updated value for each of the bit nodes.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: September 3, 2013
    Assignee: Realtek Semiconductur Corp.
    Inventors: Cheng-Kang Wang, Hou-Wei Lin, Chia-Chun Hung
  • Patent number: 8402340
    Abstract: A parity-check-code decoder includes: a verifying device that multiplies (N) bit nodes by a matrix provided with (N) columns so as to obtain a plurality of check nodes; a reliability generator that generates a reliability index for each of the bit nodes in accordance with a channel; a reliability-updating device that uses the bit nodes and the check nodes to exchange message iteratively, and following each iteration, updates (N) exchange results corresponding to the (N) columns; and a recording controller that includes a separator, a quantizing determiner and a quantizer. The separator divides the matrix into at least one column group based on the characterizing signals. The quantizing determiner determines a shift signal for each column group based on the characterizing signals. The quantizer quantizes the characterizing signals according to the shift signals for subsequent output.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: March 19, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventors: Cheng-Kang Wang, Chia-Chun Hung
  • Patent number: 7936849
    Abstract: The present invention discloses a decoding device. The decoding device includes a scaling unit for adjusting a received signal according to a scaling coefficient to generate a scaled signal; a quantizer coupled to the scaling unit for generating a quantized signal by quantizing the scaled signal; a soft decision decoder coupled to the quantizer for decoding the quantized signal to generate a decoded signal; and a scaling coefficient generating unit coupled to the scaling unit for generating the scaling coefficient according to a system information of the decoding device.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: May 3, 2011
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chun-Ming Cho, Cheng-Kang Wang, Liang-Hui Lee, Kuang-Yu Yen
  • Publication number: 20100125769
    Abstract: A parity-check-code decoder includes: a verifying device that multiplies (N) bit nodes by a matrix provided with (N) columns so as to obtain a plurality of check nodes; a reliability generator that generates a reliability index for each of the bit nodes in accordance with a channel; a reliability-updating device that uses the bit nodes and the check nodes to exchange message iteratively, and following each iteration, updates (N) exchange results corresponding to the (N) columns; and a recording controller that includes a separator, a quantizing determiner and a quantizer. The separator divides the matrix into at least one column group based on the characterizing signals. The quantizing determiner determines a shift signal for each column group based on the characterizing signals. The quantizer quantizes the characterizing signals according to the shift signals for subsequent output.
    Type: Application
    Filed: November 12, 2009
    Publication date: May 20, 2010
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Cheng-Kang WANG, Chia-Chun HUNG
  • Publication number: 20100122139
    Abstract: A parity-check-code decoder is adapted for receiving a channel quality ratio and at least (N) bits that are to be decoded. The parity-check-code decoder treats each of the bits as a bit node, and includes: a verifying circuit that multiplies (N) bit nodes by a matrix to obtain (N-K) check nodes; a reliability-generating circuit that generates a reliability index that serves as an extrinsic check index for each of the bit nodes to transmit to the check nodes; a bit exchange circuit that generates an extrinsic bit index for each of the check nodes to transmit to the bit nodes; a check-exchange circuit that updates a plurality of the extrinsic check indices based on the extrinsic bit indices for the bit nodes to transmit to the check nodes; and a reliability-updating circuit that updates the reliability index of and determines an updated value for each of the bit nodes.
    Type: Application
    Filed: November 5, 2009
    Publication date: May 13, 2010
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventors: Cheng-Kang WANG, Hou-Wei LIN, Chia-Chun HUNG
  • Publication number: 20100083074
    Abstract: A block code decoding method and device thereof are provided. The procedure of the bounded distance decoding is simplified and the number of correlation calculating is reduced via a set of pre-established XOR masks. The decoding method includes: picking up the source code part of the received message; executing a XOR calculating for the source code part with the XOR masks, and encoding the results thereof to produce a set of compared codes; executing a correlation calculating for the set of compared codes and the received message; and determining a compared code having the maximum correlation result as the decision.
    Type: Application
    Filed: September 25, 2009
    Publication date: April 1, 2010
    Applicant: Realtek Semiconductor Corp.
    Inventors: Cheng-Kang Wang, Chun-Ming Cho, Chia Chun Hung
  • Patent number: 7548594
    Abstract: An adaptive channel estimation method utilized in a multi-carrier communication system. The communication system transmits a symbol through a plurality of subchannels. The plurality of subchannels includes a plurality of pilot signal subchannels and a plurality of data signal subchannels. The pilot signal subchannels transmit a plurality of pilot signals of the symbol; the data signal subchannels transmit a plurality of data signals of the symbol. The method includes: categorizing each of the subchannels according to the relative position of each of the subchannels with respect to the pilot signal subchannels; determining channel responses of at least one of the pilot signal subchannels; and estimating channel responses of the data signal subchannels based on the channel responses of at least one of the pilot signal subchannels.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: June 16, 2009
    Assignee: Realtek Semiconductor Corp.
    Inventor: Cheng-Kang Wang
  • Publication number: 20070236370
    Abstract: The present invention discloses a decoding device. The decoding device includes a scaling unit for adjusting a received signal according to a scaling coefficient to generate a scaled signal; a quantizer coupled to the scaling unit for generating a quantized signal by quantizing the scaled signal; a soft decision decoder coupled to the quantizer for decoding the quantized signal to generate a decoded signal; and a scaling coefficient generating unit coupled to the scaling unit for generating the scaling coefficient according to a system information of the decoding device.
    Type: Application
    Filed: March 6, 2007
    Publication date: October 11, 2007
    Inventors: Chun-Ming Cho, Cheng-Kang WANG, Liang-Hui LEE, Kuang-Yu Yen
  • Publication number: 20050265466
    Abstract: An adaptive channel estimation method utilized in a multi-carrier communication system. The communication system transmits a symbol through a plurality of subchannels. The plurality of subchannels includes a plurality of pilot signal subchannels and a plurality of data signal subchannels. The pilot signal subchannels transmit a plurality of pilot signals of the symbol; the data signal subchannels transmit a plurality of data signals of the symbol. The method includes: categorizing each of the subchannels according to the relative position of each of the subchannels with respect to the pilot signal subchannels; determining channel responses of at least one of the pilot signal subchannels; and estimating channel responses of the data signal subchannels based on the channel responses of at least one of the pilot signal subchannels.
    Type: Application
    Filed: May 20, 2005
    Publication date: December 1, 2005
    Inventor: Cheng-Kang WANG