Patents by Inventor Cheng Ko

Cheng Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12255091
    Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.
    Type: Grant
    Filed: November 21, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsai-Hao Hung, Ping-Cheng Ko, Tzu-Yang Lin, Fang-Yu Liu, Cheng-Han Wu
  • Patent number: 12092700
    Abstract: An interactive test equipment for quality evaluation of resistance value test for electric leakage is disposed on a platform, and includes at least a control unit, a leaking electric current control module and an operating module. The leaking electric current control module includes at least a test set for quality evaluation to determine a resistance value for electric leakage. Each of the at least a test set has a circuit breaker and an electric leakage value display. The electric leakage value display of the each of the at least a test set can be used to display tripping circuit-breaking data of a corresponding circuit breaker. Test subjects can initiate the interactive test equipment and select answers through the operating module, and load questions and determine answers through the control unit.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: September 17, 2024
    Inventor: Po-Cheng Ko
  • Publication number: 20240280875
    Abstract: A front light module including a light guide plate, a light source, a protective cover plate, an appearance color layer, and a functional layer is provided. The light guide plate has a first surface, a second surface opposite to the first surface, and a light incident surface connecting the first surface to the second surface. The light source is disposed beside the light incident surface and configured to emit light toward the light incident surface. The protective cover plate is disposed on the first surface, and the protective cover plate has a third surface facing away from the light guide plate and a fourth surface facing the light guide plate. The appearance color layer is disposed on a portion of the third surface. The functional layer covers the appearance color layer and the third surface. An electrophoretic display device is also provided.
    Type: Application
    Filed: December 20, 2023
    Publication date: August 22, 2024
    Applicant: E Ink Holdings Inc.
    Inventors: Chih Cheng Ko, Yun-Nan Hsieh
  • Patent number: 12019217
    Abstract: An optical lens utilizing individual lenses which are, all but one, made from plastic materials but with an optical clarity unaffected by temperature swings, includes first to sixth lenses. The first to sixth lenses of the optical lens meets conditions of composite formula 4.55<|EFL2|/|EFL1|<4.95, 1.91<(N1?N3)/(N2?N3)<1.93, 0.16<(V1?V3)/(V2?V3)<0.20, 0.95<(N4?N6)/(N5?N6)<1.05 and 0.95<(V4?V6)/(V5?V6)<1.05. EFL1 is a focal length of the first to third lenses, and EFL2 is a focal length of the fourth to sixth lenses. N1, N2, N3, N4, N5, and N6 are respective refractive indexes of the first to sixth lenses, and V1, V2, V3, V4, V5, and V6 are their respective Abbe numbers.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: June 25, 2024
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ya-Lan Feng, Chun-Cheng Ko
  • Patent number: 11957262
    Abstract: A device for installing curtain gliders is revealed. The device for installing curtain gliders is a positioning strip. A plurality of gliders are arranged at the positioning strip and then carried and mounted into a curtain track by the positioning strip. The positioning strip is provided with a plurality of mounting and positioning units each of which includes a main hole, two slots disposed on two ends of the main hole, and two locking pieces located between the two slots and the main hole. Thereby the glider with different designs can be inserted into the main hole and the locking pieces are abutting against the glider for positioning the glider. Installers can assemble the gliders quickly and conveniently by count marks on the positioning strip.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: April 16, 2024
    Assignee: Carrot Industrial Co., Ltd.
    Inventors: Hsiu-Mei Hsu, Hou-Cheng Ko
  • Patent number: 11940603
    Abstract: A narrow-profile lens group for long-distance image capture includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens and a sixth lens, from object side to imaging side. Each lens has two surfaces, the group meeting formula 0.85<D/TTL<1.05, 0.37<(D*0.5)/F<0.45, where D is the maximum imaging circle diameter on the imaging surface; TTL is the distance from the center point of a surface of the first lens adjacent to the object side to the imaging surface, and F is the focal length of the telephoto lens.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: March 26, 2024
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ya-Lan Feng, Chun-Cheng Ko
  • Publication number: 20240087932
    Abstract: An apparatus having a first portion including a first front wall, a first rear wall, and a bottom wall integrally coupled to the first front wall and the first rear wall, and pivotal pin structures integrally coupled to and extending from the first rear wall. The apparatus includes a second portion having a second front wall, a second rear wall, and a top wall integrally coupled to the second front wall and the second rear wall, and pin holders integrally coupled to and extending from the second rear wall and at an offset angle with reference to the top wall. The pivotal pin structure includes a base support connected to the first rear wall and a shaft connected to the base support, and the pin holder defines an opening sized and shaped to accept the shaft. The first and second portions are sized and shaped to be pivotally movable between open and closed configurations.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Chung TSAI, Ping-Cheng KO, Fang-yu LIU, Jhih-Yuan YANG
  • Publication number: 20240087945
    Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Tsai-Hao HUNG, Ping-Cheng KO, Tzu-Yang LIN, Fang-Yu LIU, Cheng-Han WU
  • Patent number: 11881421
    Abstract: An apparatus having a first portion including a first front wall, a first rear wall, and a bottom wall integrally coupled to the first front wall and the first rear wall, and pivotal pin structures integrally coupled to and extending from the first rear wall. The apparatus includes a second portion having a second front wall, a second rear wall, and a top wall integrally coupled to the second front wall and the second rear wall, and pin holders integrally coupled to and extending from the second rear wall and at an offset angle with reference to the top wall. The pivotal pin structure includes a base support connected to the first rear wall and a shaft connected to the base support, and the pin holder defines an opening sized and shaped to accept the shaft. The first and second portions are sized and shaped to be pivotally movable between open and closed configurations.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: January 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Chung Tsai, Ping-Cheng Ko, Fang-yu Liu, Jhih-Yuan Yang
  • Patent number: 11854860
    Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsai-Hao Hung, Ping-Cheng Ko, Tzu-Yang Lin, Fang-Yu Liu, Cheng-Han Wu
  • Publication number: 20230108966
    Abstract: An interactive test equipment for quality evaluation of resistance value test for electric leakage is disposed on a platform, and includes at least a control unit, a leaking electric current control module and an operating module. The leaking electric current control module includes at least a test set for quality evaluation to determine a resistance value for electric leakage. Each of the at least a test set has a circuit breaker and an electric leakage value display. The electric leakage value display of the each of the at least a test set can be used to display tripping circuit-breaking data of a corresponding circuit breaker. Test subjects can initiate the interactive test equipment and select answers through the operating module, and load questions and determine answers through the control unit.
    Type: Application
    Filed: September 14, 2022
    Publication date: April 6, 2023
    Inventor: PO-CHENG KO
  • Publication number: 20230104801
    Abstract: An interactive test equipment for quality evaluation of power transformers includes at least a control unit, a test question type module and an operating module. The test question type module includes at least a test set, and each of the at least a test set has a transformer, a voltage value display and a resistance value display. Based on the above design, the voltage value display and the resistance value display of the each of the at least a test set can display a measured voltage value and a measured resistance value of wiring connection of a corresponding transformer. Test subjects can initiate the interactive test equipment and select answers through the operating module, and load questions and determine answers through the control unit. The interactive test equipment is used to authenticate and evaluate a judgment ability of the test subjects in order to ensure safety of a working environment.
    Type: Application
    Filed: September 14, 2022
    Publication date: April 6, 2023
    Inventor: PO-CHENG KO
  • Publication number: 20230104141
    Abstract: An interactive test equipment for quality evaluation of an insulative electric resistance value of an electric power cable at least includes a control unit, a test question type module and an operating module. The test question type module includes at least a test set. Each of the at least a test set includes at least an electric resistance value measuring part each of which has an electric voltage value display and an electric resistance value display to respectively display electric voltage values and electric resistance values of a corresponding cable. Besides, the operating module is used to initiate the interactive test equipment, to select answers, and the control unit is used to load question types and to make judgment on answers. Accordingly, test subjects are authenticated and evaluated for a judgment ability thereof in order for ensuring safety of a working environment.
    Type: Application
    Filed: September 14, 2022
    Publication date: April 6, 2023
    Inventor: PO-CHENG KO
  • Publication number: 20230077331
    Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.
    Type: Application
    Filed: November 15, 2022
    Publication date: March 16, 2023
    Inventors: Tsai-Hao HUNG, Ping-Cheng KO, Tzu-Yang LIN, Fang-Yu LIU, Cheng-Han WU
  • Patent number: 11555951
    Abstract: A display device includes a cover structure, a light guide plate, and a display panel. The cover structure includes an anti-glare layer, a light blocking frame, and an adhesive layer. The anti-glare layer has a display region and an non-display region. The light blocking frame surrounds a receiving space. An orthogonal projection of the light blocking frame on the anti-glare layer is located within the non-display region. An adhesive layer is located in the receiving space of the light blocking frame. The light guide plate is located on the surface of the adhesive layer facing away from the anti-glare layer. The display panel is adjacent to the light guide plate.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: January 17, 2023
    Assignee: E Ink Holdings Inc.
    Inventors: Chih-Cheng Ko, Yun-Nan Hsieh
  • Patent number: 11550122
    Abstract: An optical lens includes seven lenses sequentially arranged along an optical axis from an object side to an image side. A fourth lens includes a seventh surface facing the object side and an eighth surface facing the image side. Each of the seventh surface and the eighth surface includes an inflection point. The optical lens satisfies the following conditional formulas: ?0.48<tan(EFL4*log(Slope_L42))<?0.38;??conditional formula 1: 1 mm<Infp_L41_y<1.05 mm;??conditional formula 2: 0.58 mm<Infp_L42_y<0.69 mm;??condition 3: 1<(123{circumflex over (?)}T4)/(456{circumflex over (?)}Slope_L41)<1.67.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: January 10, 2023
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chun-Cheng Ko, Yi-Ting Lin
  • Patent number: 11532499
    Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsai-Hao Hung, Ping-Cheng Ko, Tzu-Yang Lin, Fang-Yu Liu, Cheng-Han Wu
  • Patent number: 11502462
    Abstract: An extension cord for polyphase voltage conversion includes a socket body, a conductive cable and a polyphase circuit disposed in the socket body. The socket body has a hollow housing, and a four-phase power connective head is disposed at an end of the housing in order to supply power to the extension cord. A breaker having safety switch function and at least two power sockets providing voltages with different phases are disposed in the housing. An end of the conductive cable is electrically connectable with a four-phase power source. The other end of the conductive cable has a four-phase power plug electrically connectable with the four-phase power connective head of the socket body. The polyphase circuit includes three phase conductors, a neutral conductor and a ground conductor. The conductors are used to electrically connect with the four-phase power connective head, the breaker and the respective at least two power sockets.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: November 15, 2022
    Inventor: Po-Cheng Ko
  • Patent number: 11500179
    Abstract: A high-resolution imaging lens proofed against high-temperature instability includes a first lens with a negative power, a second lens with a negative power, a third lens with a positive power, a fourth lens with a negative power, a fifth lens with a positive power, and a sixth lens with a positive power. The first to the sixth lenses satisfy conditions of F1<0; 0.8>|F2/F6|>0.6, F2<0, F6>0; ?3>F4/F5>?2, and 2.0<F/#. Each of the first lens, the third lens, the fourth lens, and the fifth lens is made of glass, each of the second lens and the sixth lens is made of plastic.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: November 15, 2022
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Chung Su, Chun-Cheng Ko
  • Publication number: 20220265078
    Abstract: A device for installing curtain gliders is revealed. The device for installing curtain gliders is a positioning strip. A plurality of gliders are arranged at the positioning strip and then carried and mounted into a curtain track by the positioning strip. The positioning strip is provided with a plurality of mounting and positioning units each of which includes a main hole, two slots disposed on two ends of the main hole, and two locking pieces located between the two slots and the main hole. Thereby the glider with different designs can be inserted into the main hole and the locking pieces are abutting against the glider for positioning the glider. Installers can assemble the gliders quickly and conveniently by count marks on the positioning strip.
    Type: Application
    Filed: February 19, 2021
    Publication date: August 25, 2022
    Inventors: HSIU-MEI HSU, HOU-CHENG KO