Abstract: A mother-board includes a chipset, a switch, and first and second PCI Express X16 graphics interfaces. The switch has first and second switch circuits. The switch selectively turns on one of the first and second switch circuits according to a control signal. The first PCI Express X16 graphics interface has former eight lanes electrically connected to the chipset, and latter eight lanes selectively electrically connected to the chipset through the first switch circuit. The second PCI Express X16 graphics interface has former eight lanes selectively electrically connected to the chipset through the second switch circuit. When the first switch circuit is turned on, 16 lanes of the first PCI Express X16 graphics interface are electrically connected to the chipset. When the second switch circuit is turned on, the former eight lanes of the second PCI Express X16 graphics interface are electrically connected to the chipset.

Abstract: A mother-board includes a chipset, a switch, and first and second PCI Express X16 graphics interfaces. The switch has first and second switch circuits. The switch selectively turns on one of the first and second switch circuits according to a control signal. The first PCI Express X16 graphics interface has former eight lanes electrically connected to the chipset, and latter eight lanes selectively electrically connected to the chipset through the first switch circuit. The second PCI Express X16 graphics interface has former eight lanes selectively electrically connected to the chipset through the second switch circuit. When the first switch circuit is turned on, 16 lanes of the first PCI Express X16 graphics interface are electrically connected to the chipset. When the second switch circuit is turned on, the former eight lanes of the second PCI Express X16 graphics interface are electrically connected to the chipset.

Abstract: A mother-board includes a chipset, a switch, and first and second PCI Express X16 graphics interfaces. The switch has first and second switch circuits. The switch selectively turns on one of the first and second switch circuits according to a control signal. The first PCI Express X16 graphics interface has former eight lanes electrically connected to the chipset, and latter eight lanes selectively electrically connected to the chipset through the first switch circuit. The second PCI Express X16 graphics interface has former eight lanes selectively electrically connected to the chipset through the second switch circuit. When the first switch circuit is turned on, 16 lanes of the first PCI Express X16 graphics interface are electrically connected to the chipset. When the second switch circuit is turned on, the former eight lanes of the second PCI Express X16 graphics interface are electrically connected to the chipset.

Abstract: A modularized motherboard is provided. The modularized motherboard includes a first circuit board, a second circuit board and a connecting device. The first circuit board includes a north bridge chip, a central processing unit (CPU) slot and a first connecting port. The CPU slot is coupled to the north bridge chip and is used for installing a CPU. The second circuit board is independent of the first circuit board. The second circuit board includes a second connecting port and a south bridge chip. The south bridge chip is coupled to the north bridge chip via the second connecting port the first connecting port. The connecting device is coupled between the first connecting port and the second connecting port.

Abstract: A mother-board includes a chipset, a switch, and first and second PCI Express X16 graphics interfaces. The switch has first and second switch circuits. The switch selectively turns on one of the first and second switch circuits according to a control signal. The first PCI Express X16 graphics interface has former eight lanes electrically connected to the chipset, and latter eight lanes selectively electrically connected to the chipset through the first switch circuit. The second PCI Express X16 graphics interface has former eight lanes selectively electrically connected to the chipset through the second switch circuit. When the first switch circuit is turned on, 16 lanes of the first PCI Express X16 graphics interface are electrically connected to the chipset. When the second switch circuit is turned on, the former eight lanes of the second PCI Express X16 graphics interface are electrically connected to the chipset.

Abstract: A heat sink module is used for a central processing unit (CPU). The CPU is located on a top surface of a circuit board. The heat sink module includes a heat conducting structure for conducting and radiating the heat of the CPU. The heat conducting structure goes via the circuit board and extends to a bottom surface of the circuit board.

Abstract: A power supply system includes a main power regulator, standby power regulator and automatic electronic switch. The main power regulator having a first rectifier outputs a first voltage signal to provide the main power. The standby power regulator having a second rectifier outputs a standby voltage signal to provide the standby power. The automatic electronic switch receives the standby voltage signal in response to a PSON (Power Supply ON) signal and outputs a second voltage signal to alternatively provide the main power.

Abstract: A power supply system includes a main power regulator, standby power regulator and automatic electronic switch. The main power regulator having a first rectifier outputs a first voltage signal to provide the main power. The standby power regulator having a second rectifier outputs a standby voltage signal to provide the standby power. The automatic electronic switch receives the standby voltage signal in response to a PSON (Power Supply ON) signal and outputs a second voltage signal to alternatively provide the main power.

Abstract: A data processing system includes a first central processing unit (CPU), at least one expansion port into which additional CPUs may be inserted, and a system controller. Interrupt circuitry coupled to said first CPU, said at least one expansion port, and said system controller, is configured to allow the dam processing system to operate as a multi-processor system, only one of the first and additional CPUs communicating with the system controller at any one time.