Patents by Inventor Cheng-Li Fan
Cheng-Li Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230154760Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.Type: ApplicationFiled: January 18, 2023Publication date: May 18, 2023Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen
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Patent number: 11594419Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.Type: GrantFiled: December 7, 2020Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen
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Publication number: 20220148918Abstract: A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.Type: ApplicationFiled: January 27, 2022Publication date: May 12, 2022Inventors: Kuan-Wei Huang, Cheng-Li Fan, Yu-Yu Chen
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Patent number: 11244858Abstract: A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.Type: GrantFiled: November 11, 2019Date of Patent: February 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Wei Huang, Cheng-Li Fan, Yu-Yu Chen
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Publication number: 20210118688Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.Type: ApplicationFiled: December 7, 2020Publication date: April 22, 2021Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen
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Patent number: 10861705Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.Type: GrantFiled: January 15, 2018Date of Patent: December 8, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen
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Publication number: 20200075405Abstract: A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.Type: ApplicationFiled: November 11, 2019Publication date: March 5, 2020Inventors: Kuan-Wei Huang, Cheng-Li Fan, Yu-Yu Chen
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Patent number: 10535532Abstract: Methods for patterning in a semiconductor process are described. A dummy layer is formed having a cut therein. A first sacrificial layer is formed over the dummy layer, and at least a portion of the first sacrificial layer is disposed in the cut. A second sacrificial layer is formed over the first sacrificial layer. The second sacrificial layer is patterned to have a first pattern. Using the first pattern of the second sacrificial layer, the first sacrificial layer is patterned to have the first pattern. The second sacrificial layer is removed. Thereafter, a second pattern in the first sacrificial layer is formed comprising altering a dimension of the first pattern of the first sacrificial layer. Using the second pattern of the first sacrificial layer, the dummy layer is patterned. Mask portions are formed along respective sidewalls of the patterned dummy layer. The mask portions are used to form a mask.Type: GrantFiled: July 1, 2019Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Li Fan, Chih-Hao Chen, Wen-Yen Chen
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Patent number: 10475700Abstract: A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.Type: GrantFiled: October 5, 2017Date of Patent: November 12, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Wei Huang, Cheng-Li Fan, Yu-Yu Chen
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Publication number: 20190326127Abstract: Methods for patterning in a semiconductor process are described. A dummy layer is formed having a cut therein. A first sacrificial layer is formed over the dummy layer, and at least a portion of the first sacrificial layer is disposed in the cut. A second sacrificial layer is formed over the first sacrificial layer. The second sacrificial layer is patterned to have a first pattern. Using the first pattern of the second sacrificial layer, the first sacrificial layer is patterned to have the first pattern. The second sacrificial layer is removed. Thereafter, a second pattern in the first sacrificial layer is formed comprising altering a dimension of the first pattern of the first sacrificial layer. Using the second pattern of the first sacrificial layer, the dummy layer is patterned. Mask portions are formed along respective sidewalls of the patterned dummy layer. The mask portions are used to form a mask.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventors: Cheng-Li Fan, Chih-Hao Chen, Wen-Yen Chen
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Patent number: 10347506Abstract: Methods for patterning in a semiconductor process are described. A dummy layer is formed having a cut therein. A first sacrificial layer is formed over the dummy layer, and at least a portion of the first sacrificial layer is disposed in the cut. A second sacrificial layer is formed over the first sacrificial layer. The second sacrificial layer is patterned to have a first pattern. Using the first pattern of the second sacrificial layer, the first sacrificial layer is patterned to have the first pattern. The second sacrificial layer is removed. Thereafter, a second pattern in the first sacrificial layer is formed comprising altering a dimension of the first pattern of the first sacrificial layer. Using the second pattern of the first sacrificial layer, the dummy layer is patterned. Mask portions are formed along respective sidewalls of the patterned dummy layer. The mask portions are used to form a mask.Type: GrantFiled: December 6, 2017Date of Patent: July 9, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Li Fan, Chih-Hao Chen, Wen-Yen Chen
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Publication number: 20190067022Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.Type: ApplicationFiled: January 15, 2018Publication date: February 28, 2019Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen
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Publication number: 20190067096Abstract: A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.Type: ApplicationFiled: October 5, 2017Publication date: February 28, 2019Inventors: Kuan-Wei Huang, Cheng-Li Fan, Yu-Yu Chen
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Publication number: 20190035638Abstract: Methods for patterning in a semiconductor process are described. A dummy layer is formed having a cut therein. A first sacrificial layer is formed over the dummy layer, and at least a portion of the first sacrificial layer is disposed in the cut. A second sacrificial layer is formed over the first sacrificial layer. The second sacrificial layer is patterned to have a first pattern. Using the first pattern of the second sacrificial layer, the first sacrificial layer is patterned to have the first pattern. The second sacrificial layer is removed. Thereafter, a second pattern in the first sacrificial layer is formed comprising altering a dimension of the first pattern of the first sacrificial layer. Using the second pattern of the first sacrificial layer, the dummy layer is patterned. Mask portions are formed along respective sidewalls of the patterned dummy layer. The mask portions are used to form a mask.Type: ApplicationFiled: December 6, 2017Publication date: January 31, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Li Fan, Chih-Hao Chen, Wen-Yen Chen