Patents by Inventor Cheng-Li Fan

Cheng-Li Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230154760
    Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.
    Type: Application
    Filed: January 18, 2023
    Publication date: May 18, 2023
    Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen
  • Patent number: 11594419
    Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen
  • Publication number: 20220148918
    Abstract: A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.
    Type: Application
    Filed: January 27, 2022
    Publication date: May 12, 2022
    Inventors: Kuan-Wei Huang, Cheng-Li Fan, Yu-Yu Chen
  • Patent number: 11244858
    Abstract: A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Wei Huang, Cheng-Li Fan, Yu-Yu Chen
  • Publication number: 20210118688
    Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.
    Type: Application
    Filed: December 7, 2020
    Publication date: April 22, 2021
    Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen
  • Patent number: 10861705
    Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen
  • Publication number: 20200075405
    Abstract: A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 5, 2020
    Inventors: Kuan-Wei Huang, Cheng-Li Fan, Yu-Yu Chen
  • Patent number: 10535532
    Abstract: Methods for patterning in a semiconductor process are described. A dummy layer is formed having a cut therein. A first sacrificial layer is formed over the dummy layer, and at least a portion of the first sacrificial layer is disposed in the cut. A second sacrificial layer is formed over the first sacrificial layer. The second sacrificial layer is patterned to have a first pattern. Using the first pattern of the second sacrificial layer, the first sacrificial layer is patterned to have the first pattern. The second sacrificial layer is removed. Thereafter, a second pattern in the first sacrificial layer is formed comprising altering a dimension of the first pattern of the first sacrificial layer. Using the second pattern of the first sacrificial layer, the dummy layer is patterned. Mask portions are formed along respective sidewalls of the patterned dummy layer. The mask portions are used to form a mask.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Li Fan, Chih-Hao Chen, Wen-Yen Chen
  • Patent number: 10475700
    Abstract: A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Wei Huang, Cheng-Li Fan, Yu-Yu Chen
  • Publication number: 20190326127
    Abstract: Methods for patterning in a semiconductor process are described. A dummy layer is formed having a cut therein. A first sacrificial layer is formed over the dummy layer, and at least a portion of the first sacrificial layer is disposed in the cut. A second sacrificial layer is formed over the first sacrificial layer. The second sacrificial layer is patterned to have a first pattern. Using the first pattern of the second sacrificial layer, the first sacrificial layer is patterned to have the first pattern. The second sacrificial layer is removed. Thereafter, a second pattern in the first sacrificial layer is formed comprising altering a dimension of the first pattern of the first sacrificial layer. Using the second pattern of the first sacrificial layer, the dummy layer is patterned. Mask portions are formed along respective sidewalls of the patterned dummy layer. The mask portions are used to form a mask.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: Cheng-Li Fan, Chih-Hao Chen, Wen-Yen Chen
  • Patent number: 10347506
    Abstract: Methods for patterning in a semiconductor process are described. A dummy layer is formed having a cut therein. A first sacrificial layer is formed over the dummy layer, and at least a portion of the first sacrificial layer is disposed in the cut. A second sacrificial layer is formed over the first sacrificial layer. The second sacrificial layer is patterned to have a first pattern. Using the first pattern of the second sacrificial layer, the first sacrificial layer is patterned to have the first pattern. The second sacrificial layer is removed. Thereafter, a second pattern in the first sacrificial layer is formed comprising altering a dimension of the first pattern of the first sacrificial layer. Using the second pattern of the first sacrificial layer, the dummy layer is patterned. Mask portions are formed along respective sidewalls of the patterned dummy layer. The mask portions are used to form a mask.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Li Fan, Chih-Hao Chen, Wen-Yen Chen
  • Publication number: 20190067022
    Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.
    Type: Application
    Filed: January 15, 2018
    Publication date: February 28, 2019
    Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen
  • Publication number: 20190067096
    Abstract: A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.
    Type: Application
    Filed: October 5, 2017
    Publication date: February 28, 2019
    Inventors: Kuan-Wei Huang, Cheng-Li Fan, Yu-Yu Chen
  • Publication number: 20190035638
    Abstract: Methods for patterning in a semiconductor process are described. A dummy layer is formed having a cut therein. A first sacrificial layer is formed over the dummy layer, and at least a portion of the first sacrificial layer is disposed in the cut. A second sacrificial layer is formed over the first sacrificial layer. The second sacrificial layer is patterned to have a first pattern. Using the first pattern of the second sacrificial layer, the first sacrificial layer is patterned to have the first pattern. The second sacrificial layer is removed. Thereafter, a second pattern in the first sacrificial layer is formed comprising altering a dimension of the first pattern of the first sacrificial layer. Using the second pattern of the first sacrificial layer, the dummy layer is patterned. Mask portions are formed along respective sidewalls of the patterned dummy layer. The mask portions are used to form a mask.
    Type: Application
    Filed: December 6, 2017
    Publication date: January 31, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Li Fan, Chih-Hao Chen, Wen-Yen Chen