Abstract: An LCD panel including a liquid crystal cell array, gate driving integrated circuits (ICs), first source driving ICs, second source driving ICs and a timing control circuit is provided. The liquid crystal cell array has a first display area and a second display area. The first and the second source driving ICs are electrically connected with the first and the second display areas, respectively, while the timing control circuit is electrically connected with the source and the gate driving ICs. The LCD panel is driven by writing data into the first display area through the first source driving ICs via a first receiving/transmitting mode and writing data into the second display area through the second source driving ICs via a second receiving/transmitting mode. The first data receiving/transmitting mode is different from the second receiving/transmitting mode.

Abstract: A shift registers circuit having a series of cascading shift registers comprises a first transistor coupling to an output signal of a pre-stage shift register, a second transistor coupling to the first transistor, an output and a first clock signal, and a pull-down module coupling to the output, output signals of pre-stage and post-stage shift register, a second and a third voltage level. When the second transistor turns on and the first clock signal is at high voltage level, the output is at a first voltage level. When the signal of post-stage shift register is at first voltage level, the output is at the third voltage level.

Abstract: A shift registers circuit having a series of cascading shift registers comprises a first transistor coupling to an output signal of a pre-stage shift register, a second transistor coupling to the first transistor, an output and a first clock signal, and a pull-down module coupling to the output, output signals of pre-stage and post-stage shift register, a second and a third voltage level. When the second transistor turns on and the first clock signal is at high voltage level, the output is at a first voltage level. When the signal of post-stage shift register is at first voltage level, the output is at the third voltage level.