Abstract: The present invention provides a method of preventing fluorine ions from residing in a gate to result in boron ion penetration into a gate oxide on a semiconductor wafer. A substrate, an oxide layer, a conductive layer, an anti-reflection coating (ARC), and a photoresist layer positioned on the ARC defining patterns of a gate, are formed, respectively, on the semiconductor wafer. The method first involves an etching process to remove portions of both the ARC and the conductive layer uncovered by the photoresist layer to form the gate and a gate oxide layer. After the photoresist layer is stripped, an ion implantation process is performed using the gate covered by the ARC as hard mask and boron fluoride (BF2+) as the dopant to form lightly doped drains (LDD) in the substrate adjacent to the gate. Then, a spacer is formed around the gate after the ARC is removed. Finally, the method is completed with the formation of a source and a drain in the substrate adjacent to the spacer after the ARC is stripped.

Abstract: The present invention provides a method of preventing fluorine ions from residing in a gate to result in boron ion penetration into a gate oxide on a semiconductor wafer. A substrate, an oxide layer, a conductive layer, an anti-reflection coating (ARC), and a photoresist layer positioned on the ARC defining patterns of a gate, are formed, respectively, on the semiconductor wafer. The method first involves an etching process to remove portions of both the ARC and the conductive layer uncovered by the photoresist layer to form the gate and a gate oxide layer. After the photoresist layer is stripped, an ion implantation process is performed using the gate covered by the ARC as hard mask and boron fluoride (BF2+) as the dopant to form lightly doped drains (LDD) in the substrate adjacent to the gate. Then, a spacer is formed around the gate after the ARC is removed. Finally, the method is completed with the formation of a source and a drain in the substrate adjacent to the spacer after the ARC is stripped.

Abstract: A method of increasing the operating speed of an SRAM device. The SRAM device is constructed from a plurality of loads and a plurality of NMOS transistors. A positive voltage is applied to the substrate of the NMOS transistors when data needs to be read from the SRAM device or written to the SRAM device. The positive voltage increases the channel width between the source and the drain terminal of the NMOS transistors so that a higher current is produced and operating speed of the device is increased. An earth voltage is applied to the substrate when the SRAM device is in a standby mode to prevent current leakage.