Patents by Inventor Cheng-Lung Chen
Cheng-Lung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240405129Abstract: An electronic device is provided. The electronic device includes a substrate, a material layer, a first metal layer, and a second metal layer. The material layer is disposed on the substrate, wherein a material of the material layer includes polysilicon, amorphous silicon, or indium gallium zinc oxide. The first metal layer is disposed on the material layer, wherein a first edge of the first metal layer includes a first curved portion. The second metal layer is disposed on the material layer, wherein a second edge of the second metal layer includes a second curved portion, and the second edge surrounds the first edge.Type: ApplicationFiled: August 8, 2024Publication date: December 5, 2024Inventors: Chin-Lung TING, Cheng-Hsu CHOU, Ming-Chun TSENG, Yun-Sheng CHEN, Chih-Hsiung CHANG, Liang-Lu CHEN
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Patent number: 12159812Abstract: A method of forming a semiconductor device includes following steps. A first organic layer is formed to cover a first conductive layer. A first opening is formed in the first organic layer to expose a first surface of the first conductive layer. A first silicon layer is formed on a sidewall of the first opening and the first surface of the first conductive layer. A first dielectric layer is formed on the sidewall of the first opening and the first surface of the first conductive layer over the first silicon layer. By using a first mask, portions of the first silicon layer and the first dielectric layer on the first surface are simultaneously removed to expose the first surface, wherein after removing the portions of the first silicon layer and the first dielectric layer, the first dielectric layer covers a top surface of the first silicon layer.Type: GrantFiled: May 30, 2022Date of Patent: December 3, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Lung Yang, Chih-Hung Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
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Patent number: 12151324Abstract: The present disclosure relates to methods for inserting a fastener into a wafer-carrying pod. The system includes a robotic arm with a screw tool assembly disposed at the far end of the robotic arm. The screw tool assembly includes a lower sleeve configured to receive a fastener. A screwdriver is disposed within an upper sleeve of the screw tool assembly, and a motor is provided to rotate the screwdriver. In use, the screw tool assembly is positioned over the fastener so the lower sleeve surrounds the fastener and the screwdriver engages the fastener. The fastener head is received within the lower sleeve, and the screwdriver screws the fastener into the pod.Type: GrantFiled: May 19, 2023Date of Patent: November 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chen Chen, Chih-Hung Huang, Cheng-Lung Wu, Yang-Ann Chu, Jiun-Rong Pai
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Publication number: 20240383082Abstract: The present disclosure relates to systems and methods for affixing and/or removing a fastener from a wafer-carrying pod. The system includes a robotic arm with a screw tool assembly disposed at the far end of the robotic arm. The screw tool assembly includes a lower sleeve configured to receive a fastener. A screwdriver is disposed within an upper sleeve of the screw tool assembly, and a motor is provided to rotate the screwdriver. In use, the screw tool assembly is positioned over the fastener so the lower sleeve surrounds the fastener and the screwdriver engages the fastener. The screwdriver unscrews the fastener from the pod, and the fastener head is received within the lower sleeve.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Inventors: Yu-Chen Chen, Chih-Hung Huang, Cheng-Lung Wu, Yang-Ann Chu, Jiun-Rong Pai
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Publication number: 20240387586Abstract: One or more semiconductor processing tools may deposit a contact etch stop layer on a substrate. In some implementations, the contact etch stop layer is comprised of less than approximately 12 percent hydrogen. Depositing the contact etch stop layer may include depositing contact etch stop layer material at a temperature of greater than approximately 600 degrees Celsius, at a pressure of greater than approximately 150 torr, and/or with a ratio of at least approximately 70:1 of NH3 and SiH4, among other examples. The one or more semiconductor processing tools may deposit a silicon-based layer above the contact etch stop layer. The one or more semiconductor processing tools may perform an etching operation into the silicon-based layer until reaching the contact etch stop layer to form a trench isolation structure.Type: ApplicationFiled: July 26, 2024Publication date: November 21, 2024Inventors: Cheng-Hsien CHEN, Yung-Hsiang CHEN, Chia Hao LI, Yu-Lung YEH, Yen-Hsiu CHEN
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Publication number: 20240387644Abstract: Ruthenium of a metal gate (MG) and/or a middle end of line (MEOL) structure is annealed to reduce, or even eliminate, seams after the ruthenium is deposited. Because the annealing reduces (or removes) seams in deposited ruthenium, electrical performance is increased because resistivity of the MG and/or the MEOL structure is decreased. Additionally, for MGs, the annealing generates a more even deposition profile, which results in a timed etching process producing a uniform gate height. As a result, more of the MGs will be functional after etching, which increases yield during production of the electronic device.Type: ApplicationFiled: July 24, 2024Publication date: November 21, 2024Inventors: Hsin-Han TSAI, Hsiang-Ju LIAO, Yi-Lun LI, Cheng-Lung HUNG, Weng CHANG, Chi On CHUI, Jo-Chun HUNG, Chih-Wei LEE, Chia-Wei CHEN
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Publication number: 20240379391Abstract: An airflow detection device is capable of detecting airflow issues associated with a transport carrier, such as a blockage of a diffuser in a transport carrier or leakage of a transition bracket, among other examples. The airflow detection device includes an air tunnel through which a gas in a transport carrier may flow. The airflow detection device includes an airflow sensor configured to generate airflow data based on a flow of the gas through the air tunnel. In some implementations, the airflow detection device is included in an airflow detection system to perform automated measurements and to determine, identify, and/or detect airflow issues associated with a transport carrier. In this way, the airflow detection system may perform one or more automated actions (or may cause one or more other devices to perform one or more automated actions) based on a detection of a diffuser blockage or a transition bracket leak.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Inventors: Yu-Chen CHEN, Cheng-Lung WU, Yang-Ann CHU, Jiun-Rong PAI, Ren-Hau WU
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Publication number: 20240379811Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The second layer includes metal and oxygen. The first layer is first layer over the gate dielectric layer and may include one of titanium nitride (TiN), titanium silicon nitride (TiSiN), or tantalum carbide (TaC). Minimization of equivalent oxide thickness may result.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: Yong-Tian Hou, Yuan-Shun Chao, Chien-Hao Chen, Cheng-Lung Hung
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Publication number: 20240371680Abstract: A semiconductor arrangement includes an isolation structure having a first electrical insulator layer in a trench in a semiconductor substrate and a second electrical insulator layer in the trench and over the first electrical insulator layer.Type: ApplicationFiled: July 19, 2024Publication date: November 7, 2024Inventors: Wei-Liang CHEN, Cheng-Hsien CHEN, Yu-Lung YEH, Chuang CHIHCHOUS, Yen-Hsiu CHEN
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Patent number: 12132112Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a nanostructured channel region disposed on the fin structure, and a gate-all-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes a high-K (HK) gate dielectric layer with a metal doped region having dopants of a first metallic material, a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer, a bimetallic nitride layer interposed between the HK gate dielectric layer and the pWFM layer, an n-type work function metal (nWFM) layer disposed on the pWFM layer, and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metallic material and the bimetallic nitride layer includes the first and second metallic materials.Type: GrantFiled: July 28, 2022Date of Patent: October 29, 2024Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Ji-Cheng Chen, Weng Chang, Chi On Chui
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Publication number: 20240347571Abstract: A semiconductor device is provided. The semiconductor device includes a first deep trench isolation (DTI) structure within a substrate. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is between the barrier structure and the copper structure. The barrier structure is between the substrate and the dielectric structure.Type: ApplicationFiled: June 27, 2024Publication date: October 17, 2024Inventors: Yung-Hsiang CHEN, Yu-Lung YEH, Yen-Hsiu CHEN, Bo-Chang SU, Cheng-Hsien CHEN
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Publication number: 20240347636Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a nanostructured channel region disposed on the fin structure, and a gate-all-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes a high-K (HK) gate dielectric layer with a metal doped region having dopants of a first metallic material, a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer, a bimetallic nitride layer interposed between the HK gate dielectric layer and the pWFM layer, an n-type work function metal (nWFM) layer disposed on the pWFM layer, and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metallic material and the bimetallic nitride layer includes the first and second metallic materials.Type: ApplicationFiled: June 26, 2024Publication date: October 17, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Yi LEE, Cheng-Lung HUNG, Ji-Cheng CHEN, Weng CHANG, Chi On CHUI
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Patent number: 12119251Abstract: A multiple die container load port may include a housing with an opening, and an elevator to accommodate a plurality of different sized die containers. The multiple die container load port may include a stage supported by the housing and moveable within the opening of the housing by the elevator. The stage may include one or more positioning mechanisms to facilitate positioning of the plurality of different sized die containers on the stage, and may include different portions movable by the elevator to accommodate the plurality of different sized die containers. The multiple die container load port may include a position sensor to identify one of the plurality of different sized die containers positioned on the stage.Type: GrantFiled: January 7, 2022Date of Patent: October 15, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hung Huang, Cheng-Lung Wu, Yi-Fam Shiu, Yu-Chen Chen, Yang-Ann Chu, Jiun-Rong Pai
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Patent number: 12094983Abstract: A display device is provided. The display device includes a substrate, a channel layer, a first metal layer, and a second metal layer. The channel layer is disposed on the substrate and includes a first channel layer and a second channel layer. The first metal layer is disposed on the channel layer and includes a first gate and a second gate. The second metal layer is disposed over the first metal layer and includes a first source, a first drain, and a second source. The first gate, the first source, the first drain, and the first channel layer form a first transistor. The second gate, the second source, the first drain, and the second channel layer form a second transistor. The first transistor and the second transistor are connected in parallel.Type: GrantFiled: October 19, 2021Date of Patent: September 17, 2024Assignee: INNOLUX CORPORATIONInventors: Chin-Lung Ting, Cheng-Hsu Chou, Ming-Chun Tseng, Yun-Sheng Chen, Chih-Hsiung Chang, Liang-Lu Chen
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Patent number: 12094756Abstract: A semiconductor arrangement includes an isolation structure having a first electrical insulator layer in a trench in a semiconductor substrate and a second electrical insulator layer in the trench and over the first electrical insulator layer.Type: GrantFiled: July 27, 2022Date of Patent: September 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Wei-Liang Chen, Cheng-Hsien Chen, Yu-Lung Yeh, Chuang Chihchous, Yen-Hsiu Chen
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Patent number: 12080575Abstract: An airflow detection device is capable of detecting airflow issues associated with a transport carrier, such as a blockage of a diffuser in a transport carrier or leakage of a transition bracket, among other examples. The airflow detection device includes an air tunnel through which a gas in a transport carrier may flow. The airflow detection device includes an airflow sensor configured to generate airflow data based on a flow of the gas through the air tunnel. In some implementations, the airflow detection device is included in an airflow detection system to perform automated measurements and to determine, identify, and/or detect airflow issues associated with a transport carrier. In this way, the airflow detection system may perform one or more automated actions (or may cause one or more other devices to perform one or more automated actions) based on a detection of a diffuser blockage or a transition bracket leak.Type: GrantFiled: June 17, 2021Date of Patent: September 3, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chen Chen, Cheng-Lung Wu, Yang-Ann Chu, Jiun-Rong Pai, Ren-Hau Wu
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Publication number: 20240273759Abstract: A method for determining a pose of a target object is to be implemented by a computing device that stores a database related to a specific type of object. The database includes a plurality of template images. The method includes: obtaining an input image that contains the target object belonging to the specific type; selecting a matching image that best matches with the input image from among the template images; performing a keypoint matching procedure to identify a plurality of first feature points that are related an the appearance of the target object shown in the input image, and a plurality of second feature points that are shown in the matching image and that respectively match with the first feature points; and generating a pose-determination result that indicates the pose of the target object based on relationships among the first feature points and the second feature points.Type: ApplicationFiled: January 24, 2024Publication date: August 15, 2024Applicant: SOLOMON TECHNOLOGY CORPORATIONInventors: Cheng-Lung CHEN, Xuan Loc NGUYEN, Tafjira Nugraha BRILIAN, Manh Quan NGUYEN, Chieh TSAI
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Patent number: 12051659Abstract: Semiconductor devices are provided. The semiconductor device includes a substrate, an interconnect structure, and a conductive pad structure. The interconnect structure is over the substrate and includes a top metal layer. The conductive pad structure is over the interconnect structure and includes a lower barrier film, an upper barrier film, and an aluminum-containing layer. The lower barrier film is on the top metal layer. The upper barrier film is on the lower barrier film and has an amorphous structure. The aluminum-containing layer is on the upper barrier film. The lower barrier film and the upper barrier film are made of a same material, and a nitrogen atomic percentage of the upper barrier film is higher than a nitrogen atomic percentage of the lower barrier film.Type: GrantFiled: May 10, 2023Date of Patent: July 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hsun Huang, Po-Han Wang, Ing-Ju Lee, Chao-Lung Chen, Cheng-Ming Wu
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Publication number: 20240249494Abstract: An environment managing and monitoring system and a method using same are provided. The environment managing and monitoring system is configured to assist monitors to obtain real-time information of the monitoring field and control device in the monitoring field. The environmental managing and monitoring system includes at least one sub-system and a host system. The host system is configured to output a region of interest condition and a monitoring condition to the sub-system, wherein the sub-system is configured to generate monitoring results according to the monitoring conditions, and selects an image range from the captured wide-angle dynamic real-time images according to the region of interest condition.Type: ApplicationFiled: September 4, 2023Publication date: July 25, 2024Inventors: Yung-tai SU, Hsin-lung HSIEH, Yu-hsuan LIAO, Yu-min CHUANG, Pang-tzu LIU, Chun-yueh CHEN, Jia-hao LU, Cheng-ju HSUIEH, Ching-wei LEE, Tsung-hsun TSAI, Po-yuan KUO, Po-yi WU, Chen-wei CHOU
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Patent number: D1040719Type: GrantFiled: July 25, 2019Date of Patent: September 3, 2024Assignee: Chris Cam Industry Inc.Inventors: Cheng-Chung Chen, Hung-Lung Chen