Patents by Inventor Cheng-Lung Lu

Cheng-Lung Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and pattern for avoiding micro-loading effect in an etching process
    Patent number: 6150678
    Abstract: A method for avoiding micro-loading effect during etching is disclosed. The method comprises the steps of: providing a semiconductor substrate with a layer to be patterned and etched formed thereover; forming a masking layer over the layer to be patterned; defining a row pattern in the masking layer, the row pattern comprising a plurality of rectangles and a plurality of connecting bars, each of the connecting bars connecting two of the rectangles; and removing a portion of the layer to be patterned, to form a patterned layer with a recessed channel, by using the masking layer as a mask with the row pattern.
    Type: Grant
    Filed: February 11, 1999
    Date of Patent: November 21, 2000
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chia-Ching Tung, Cheng-Lung Lu, Hung-Yi Luo