Abstract: A method of unlocking a vehicle door, including generating a dynamic password based on dynamic information by a vehicle chip, then generating a reference key based on the dynamic password, and storing the reference key in a storage medium; updating the dynamic password stored in a server, and according to the request of the mobile device, providing the dynamic password to the mobile device through the server, and the mobile device generating a mobile key according to the dynamic password. Finally, the reference key and the mobile key are compared, and if the dynamic passwords corresponding to the reference key and the mobile key are the same, the vehicle door corresponding to the vehicle chip is unlocked by the vehicle chip.

Abstract: The disclosure provides a method of unlocking a vehicle door, including generating a dynamic password based on dynamic information by a vehicle chip, then generating a reference key based on the dynamic password, and storing the reference key in a storage medium; updating the dynamic password stored in a server, and according to the request of the mobile device, providing the dynamic password to the mobile device through the server, and the mobile device generating a mobile key according to the dynamic password. Finally, the reference key and the mobile key are compared, and if the dynamic passwords corresponding to the reference key and the mobile key are the same, the vehicle door corresponding to the vehicle chip is unlocked by the vehicle chip.

Abstract: A method of antenna deployment determination in a wireless communication device is disclosed. The method includes transceiving a radio signal via the a first antenna port of the wireless communication device, obtaining a first strength result corresponding to the radio signal transmitted or received via the first antenna port, and determining a connecting status of the first antenna port according to the first strength result.

Abstract: An electronic device and an associated method are provided. The electronic device includes a wireless circuit and a controller. The wireless circuit is arranged to provide a soft access point. The controller is arranged to detect whether there is at least one client trying to connect to the soft access point when the electronic device operates in a sleep mode; and allow the electronic device to enter a working mode from the sleep mode when detecting that there is at least one client trying to connect to the soft access point.

Abstract: Methods and systems for design of integrated circuits including performing OPC are discussed. In one embodiment, design data having a geometric feature is provided. A base feature is formed from the geometric feature, which has a substantially linear edge. A pseudo dissection point is determined on the base feature. Add or trim a polygon from the base feature to form a modified feature. An OPC process is performed on the modified feature to generate an output design. The output design is used to fabricate a semiconductor device on a semiconductor substrate.

Abstract: Methods and systems for design of integrated circuits including performing OPC are discussed. In one embodiment, design data having a geometric feature is provided. A base feature is formed from the geometric feature, which has a substantially linear edge. A pseudo dissection point is determined on the base feature. Add or trim a polygon from the base feature to form a modified feature. An OPC process is performed on the modified feature to generate an output design. The output design is used to fabricate a semiconductor device on a semiconductor substrate.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes building a pattern bank including a pattern having an area of interest. The method further includes recognizing that the pattern of the pattern bank corresponds to a pattern of an IC design layout. The method further includes identifying an area of interest of the pattern of the IC design layout that corresponds to the area of interest of the pattern of the pattern bank. The method further includes performing pattern recognition dissection on the area of interest of the pattern of the IC design layout to dissect the area of interest of the pattern of the IC design layout into a plurality of segments. The method further includes after performing pattern recognition dissection, producing a modified IC design layout.

Abstract: The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node.

Abstract: The present disclosure describes methods of forming a mask. In an example, the method includes receiving an integrated circuit (IC) design layout, modifying the IC design layout data using an optical proximity correction (OPC) process, thereby providing an OPCed IC design layout, and modifying the OPCed IC design layout data using a mask rule check (MRC) process, wherein the MRC process corrects rule violations of the OPCed IC design layout data using a mask error enhancement factor (MEEF) index, thereby providing a MRC/OPCed IC design layout.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes building a pattern bank including a pattern having an area of interest. The method further includes recognizing that the pattern of the pattern bank corresponds to a pattern of an IC design layout. The method further includes identifying an area of interest of the pattern of the IC design layout that corresponds to the area of interest of the pattern of the pattern bank. The method further includes performing pattern recognition dissection on the area of interest of the pattern of the IC design layout to dissect the area of interest of the pattern of the IC design layout into a plurality of segments. The method further includes after performing pattern recognition dissection, producing a modified IC design layout.

Abstract: An electronic device including a bio-polymer material and a method for manufacturing the same are disclosed. The electronic device of the present invention comprises: a substrate; a first electrode disposed on the substrate; a bio-polymer layer disposed on the first electrode, wherein the bio-polymeric material is selected from a group consisting of wool keratin, collagen hydrolysate, gelatin, whey protein and hydroxypropyl methylcellulose; and a second electrode disposed on the biopolymer material layer. The present invention is suitable for various electronic devices such as an organic thin film transistor, an organic floating gate memory, or a metal-insulator-metal capacitor.

Abstract: A method of manufacturing plastic metallized 3D circuit includes the steps of providing a 3D plastic main body; performing a surface pretreatment on the plastic main body; performing a metallization process on the plastic main body to deposit a thin metal film thereon; performing a photoresist coating process to form a photoresist protective layer on the thin metal film; performing an exposure and development process on the photoresist protective layer to form a patterned photoresist protective layer; performing an etching process on the exposed thin metal film to form a patterned metal circuit layer; stripping the patterned photoresist protective layer; and performing a surface treatment on the patterned metal circuit layer to form a metal protective layer. With the method, a 3D circuit pattern can be directly formed on a 3D plastic main body without providing additional circuit carrier to thereby meet the requirement for miniaturized and compact electronic devices.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.

Abstract: Instead of scanning all the channels at once, the present method separates a channel scanning procedure into multiple channel scanning operations. The method reduces a data loss rate during the operation by returning to the operating channel an associated access point operates on in accordance with a return period for transceiving blocked packets.

Abstract: The present disclosure provides an integrated circuit method. The method includes providing an integrated circuit (IC) design layout; simulating thermal effect to the IC design layout; simulating electrical performance to the IC design layout based on the simulating thermal effect; and performing thermal dummy insertion to the IC design layout based on the simulating electrical performance.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.

Abstract: The present disclosure provides an integrated circuit method. The method includes providing an integrated circuit (IC) design layout; simulating thermal effect to the IC design layout; simulating electrical performance to the IC design layout based on the simulating thermal effect; and performing thermal dummy insertion to the IC design layout based on the simulating electrical performance.

Abstract: An integrated circuit (IC) design method providing a circuit design layout having a plurality of functional blocks disposed a distance away from each other; identifying a local pattern density to an approximate dummy region, on the circuit design layout, within a predefined distance to one of the functional blocks; performing a local dummy insertion to the approximate dummy region according to the local pattern density; repeating the identifying and performing to at least some other of the functional blocks; and implementing a global dummy insertion to a non-local dummy region according to a global pattern density.

Abstract: The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node.

Abstract: An apparatus for roaming in a wireless network updates received signal strength indication (RSSI) values in accordance with all types of frames forwarded from the access point with which the apparatus associates. In addition, the apparatus actively forwards null frames to the access point with which the apparatus associates and updates RSSI values in accordance with acknowledgement frames forwarded from the access point.