Patents by Inventor Cheng-Lung Tsai
Cheng-Lung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11951569Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.Type: GrantFiled: May 12, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Ming Wu, Yung-Lung Lin, Hau-Yi Hsiao, Sheng-Chau Chen, Cheng-Yuan Tsai
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Publication number: 20240113071Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.Type: ApplicationFiled: January 5, 2023Publication date: April 4, 2024Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
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Patent number: 11942451Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.Type: GrantFiled: August 30, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Yen Chang, Yu-Chia Lai, Cheng-Shiuan Wong, Ting Hao Kuo, Ching-Hua Hsieh, Hao-Yi Tsai, Kuo-Lung Pan, Hsiu-Jen Lin
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Patent number: 11935957Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.Type: GrantFiled: August 9, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Publication number: 20240067512Abstract: An automatic fluid replacement device is adapted to be mounted on an opening of a storage barrel. The automatic fluid replacement device includes a robotic arm, at least one fluid convey joint and a controller. The robotic arm has a gripper. The fluid convey joint includes a convey pipe, a sleeve and a sealing bag. The convey pipe is configured to deliver a fluid. The sleeve is sleeved on the convey pipe. The gripper clamps the sleeve. The sealing bag is sleeved on the sleeve. The controller is configured for automatically controlling the robotic arm to move the fluid convey joint into the opening and controlling the sealing bag to be inflated to seal the opening.Type: ApplicationFiled: October 27, 2022Publication date: February 29, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Cheng-Han TSAI, Wei-Lung PAN, Chih-Ta WU, I-hsin LIN
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Patent number: 9692532Abstract: A method of antenna deployment determination in a wireless communication device is disclosed. The method includes transceiving a radio signal via the a first antenna port of the wireless communication device, obtaining a first strength result corresponding to the radio signal transmitted or received via the first antenna port, and determining a connecting status of the first antenna port according to the first strength result.Type: GrantFiled: November 2, 2012Date of Patent: June 27, 2017Assignee: MEDIATEK INC.Inventors: Yu-Ju Lee, Cheng-Lung Tsai, Hao-Sheng Hsu, Hui-Kuang Tseng
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Publication number: 20150358906Abstract: An electronic device and an associated method are provided. The electronic device includes a wireless circuit and a controller. The wireless circuit is arranged to provide a soft access point. The controller is arranged to detect whether there is at least one client trying to connect to the soft access point when the electronic device operates in a sleep mode; and allow the electronic device to enter a working mode from the sleep mode when detecting that there is at least one client trying to connect to the soft access point.Type: ApplicationFiled: May 26, 2015Publication date: December 10, 2015Inventors: Kuo-Pin Chiou, Cheng-Lung Tsai
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Patent number: 9189588Abstract: Methods and systems for design of integrated circuits including performing OPC are discussed. In one embodiment, design data having a geometric feature is provided. A base feature is formed from the geometric feature, which has a substantially linear edge. A pseudo dissection point is determined on the base feature. Add or trim a polygon from the base feature to form a modified feature. An OPC process is performed on the modified feature to generate an output design. The output design is used to fabricate a semiconductor device on a semiconductor substrate.Type: GrantFiled: December 10, 2013Date of Patent: November 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Li Cheng, Ming-Hui Chih, Yu-Po Tang, Chia-Ping Chiang, Cheng-Lung Tsai, Sheng-Wen Lin, Kuei-Liang Lu, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20150161321Abstract: Methods and systems for design of integrated circuits including performing OPC are discussed. In one embodiment, design data having a geometric feature is provided. A base feature is formed from the geometric feature, which has a substantially linear edge. A pseudo dissection point is determined on the base feature. Add or trim a polygon from the base feature to form a modified feature. An OPC process is performed on the modified feature to generate an output design. The output design is used to fabricate a semiconductor device on a semiconductor substrate.Type: ApplicationFiled: December 10, 2013Publication date: June 11, 2015Inventors: Wen-Li Cheng, Ming-Hui Chih, Yu-Po Tang, Chia-Ping Chiang, Cheng-Lung Tsai, Sheng-Wen Lin, Kuei-Liang Lu, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 8751976Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes building a pattern bank including a pattern having an area of interest. The method further includes recognizing that the pattern of the pattern bank corresponds to a pattern of an IC design layout. The method further includes identifying an area of interest of the pattern of the IC design layout that corresponds to the area of interest of the pattern of the pattern bank. The method further includes performing pattern recognition dissection on the area of interest of the pattern of the IC design layout to dissect the area of interest of the pattern of the IC design layout into a plurality of segments. The method further includes after performing pattern recognition dissection, producing a modified IC design layout.Type: GrantFiled: June 27, 2012Date of Patent: June 10, 2014Inventors: Cheng-Lung Tsai, Jui-Hsuan Feng, Sheng-Wen Lin, Wen-Li Cheng, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 8745554Abstract: The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node.Type: GrantFiled: December 28, 2009Date of Patent: June 3, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Chou Cheng, Tsong-Hua Ou, Josh J. H. Feng, Cheng-Lung Tsai, Ru-Gun Liu, Wen-Chun Huang
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Patent number: 8739080Abstract: The present disclosure describes methods of forming a mask. In an example, the method includes receiving an integrated circuit (IC) design layout, modifying the IC design layout data using an optical proximity correction (OPC) process, thereby providing an OPCed IC design layout, and modifying the OPCed IC design layout data using a mask rule check (MRC) process, wherein the MRC process corrects rule violations of the OPCed IC design layout data using a mask error enhancement factor (MEEF) index, thereby providing a MRC/OPCed IC design layout.Type: GrantFiled: October 4, 2012Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Lung Tsai, Jui-Hsuan Feng, Sheng-Wen Lin, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20140007024Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes building a pattern bank including a pattern having an area of interest. The method further includes recognizing that the pattern of the pattern bank corresponds to a pattern of an IC design layout. The method further includes identifying an area of interest of the pattern of the IC design layout that corresponds to the area of interest of the pattern of the pattern bank. The method further includes performing pattern recognition dissection on the area of interest of the pattern of the IC design layout to dissect the area of interest of the pattern of the IC design layout into a plurality of segments. The method further includes after performing pattern recognition dissection, producing a modified IC design layout.Type: ApplicationFiled: June 27, 2012Publication date: January 2, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Lung Tsai, Jui-Hsuan Feng, Sheng-Wen Lin, Wen-Li Cheng, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20130181191Abstract: An electronic device including a bio-polymer material and a method for manufacturing the same are disclosed. The electronic device of the present invention comprises: a substrate; a first electrode disposed on the substrate; a bio-polymer layer disposed on the first electrode, wherein the bio-polymeric material is selected from a group consisting of wool keratin, collagen hydrolysate, gelatin, whey protein and hydroxypropyl methylcellulose; and a second electrode disposed on the biopolymer material layer. The present invention is suitable for various electronic devices such as an organic thin film transistor, an organic floating gate memory, or a metal-insulator-metal capacitor.Type: ApplicationFiled: June 1, 2012Publication date: July 18, 2013Inventors: Jenn-Chang Hwang, Chao-Ying Hsieh, Lung-Kai Mao, Chun-Yi Lee, Li-Shiuan Tsai, Cheng-Lung Tsai, Wei-Cheng Chung, Ping-Chiang Lyu
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Publication number: 20130126465Abstract: A method of manufacturing plastic metallized 3D circuit includes the steps of providing a 3D plastic main body; performing a surface pretreatment on the plastic main body; performing a metallization process on the plastic main body to deposit a thin metal film thereon; performing a photoresist coating process to form a photoresist protective layer on the thin metal film; performing an exposure and development process on the photoresist protective layer to form a patterned photoresist protective layer; performing an etching process on the exposed thin metal film to form a patterned metal circuit layer; stripping the patterned photoresist protective layer; and performing a surface treatment on the patterned metal circuit layer to form a metal protective layer. With the method, a 3D circuit pattern can be directly formed on a 3D plastic main body without providing additional circuit carrier to thereby meet the requirement for miniaturized and compact electronic devices.Type: ApplicationFiled: December 30, 2011Publication date: May 23, 2013Applicants: ICT-LANTO LIMITEDInventors: Chuan Ling HU, Cheng Lung TSAI, Yu Wei CHEN, Chen Hao CHANG
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Patent number: 8381153Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.Type: GrantFiled: September 17, 2010Date of Patent: February 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ping Chiang, Yu-Po Tang, Ming-Hui Chih, Cheng-Kun Tsai, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau, Cheng-Lung Tsai, Josh J. H. Feng, Bing-Syun Yeh, Jeng-Shiun Ho, Cheng-Cheng Kuo
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Patent number: 8228807Abstract: Instead of scanning all the channels at once, the present method separates a channel scanning procedure into multiple channel scanning operations. The method reduces a data loss rate during the operation by returning to the operating channel an associated access point operates on in accordance with a return period for transceiving blocked packets.Type: GrantFiled: July 23, 2009Date of Patent: July 24, 2012Assignee: Ralink Technology CorporationInventors: Cheng Lung Tsai, Sung Chien Tang
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Patent number: 8219951Abstract: The present disclosure provides an integrated circuit method. The method includes providing an integrated circuit (IC) design layout; simulating thermal effect to the IC design layout; simulating electrical performance to the IC design layout based on the simulating thermal effect; and performing thermal dummy insertion to the IC design layout based on the simulating electrical performance.Type: GrantFiled: February 26, 2010Date of Patent: July 10, 2012Assignee: Taiwan Semiconductor Manufactuing Company, Ltd.Inventors: Ying-Chou Cheng, Tsong-Hua Ou, Chih-Wei Hsu, Cheng-Lung Tsai, Ru-Gun Liu, Wen-Chun Huang, Boren Luo
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Publication number: 20120072874Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.Type: ApplicationFiled: September 17, 2010Publication date: March 22, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ping Chiang, Yu-Po Tang, Ming-Hui Chih, Cheng-Kun Tsai, Wei-Long Wang, Wen-Chun Huang, Ru-Gun Liu, Tsai-Sheng Gau, Cheng-Lung Tsai, Josh J.H. Feng, Bing-Syun Yeh, Jeng-Shiun Ho, Cheng-Cheng Kuo
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Publication number: 20110214101Abstract: The present disclosure provides an integrated circuit method. The method includes providing an integrated circuit (IC) design layout; simulating thermal effect to the IC design layout; simulating electrical performance to the IC design layout based on the simulating thermal effect; and performing thermal dummy insertion to the IC design layout based on the simulating electrical performance.Type: ApplicationFiled: February 26, 2010Publication date: September 1, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ying-Chou Cheng, Tsong-Hua Ou, Chih-Wei Hsu, Cheng-Lung Tsai, Ru-Gun Liu, Wen-Chun Huang, Boren Luo