Patents by Inventor Cheng-Lung Yang

Cheng-Lung Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240103577
    Abstract: In one example, an electronic device may include a main body, and a back cover having an opening. The back cover may include an inner surface, and a hook protruding from the inner surface. The hook may be engageable with a receiving portion of the main body to slidably couple the back cover to the main body. Further, electronic device may include a component housing connected to the main body through the opening in the back cover to fixedly couple the back cover to the main body.
    Type: Application
    Filed: November 5, 2019
    Publication date: March 28, 2024
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Cheng-Yi Yang, Szu Tao Tong, Hai-Lung Hung
  • Publication number: 20240021499
    Abstract: Some devices included a substrate; and a through via, including a plurality of scallops adjacent the through via in a first region and a plurality of scallops adjacent the through via in a second region, the of scallops having a first depth, the scallops having a greater depth. Some devices include an opening extending into a substrate, including a first region and a second region. Sidewalls of the opening include a stack of first concave portions extending a first distance into the first substrate, and a stack of second concave portions extending a second distance, greater than and parallel to the first distance, into the first substrate. A conductor partially fills the first concave portions and at least partially fills the respective second concave portions.
    Type: Application
    Filed: July 31, 2023
    Publication date: January 18, 2024
    Inventors: Hsu-Lun Liu, Wen-Hsiung Lu, Ming-Da Cheng, Chen-En Yen, Cheng-Lung Yang, Kuanchih Huang
  • Publication number: 20240014105
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes at least one substrate and an interconnection structure. The at least one substrate has a cavity partially defined by an inner sidewall of the at least one substrate and a channel disposed at a bottom of the at least one substrate. The channel laterally penetrates through the at least one substrate. The interconnections structure is disposed over the substrate, and the interconnection structure has a through hole penetrating through the interconnection structure. The through hole, the cavity and the channel are in spatial communication with each other.
    Type: Application
    Filed: September 22, 2023
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Sheng Lin, Cheng-Lung Yang, Chin-Yu Ku, Ming-Da Cheng, Wen-Hsiung Lu, Tang-Wei Huang, Fu Wei Liu
  • Patent number: 11776881
    Abstract: A through via comprising sidewalls having first scallops in a first region and second scallops in a second region and a method of forming the same are disclosed. In an embodiment, a semiconductor device includes a first substrate; and a through via extending through the substrate, the substrate including a first plurality of scallops adjacent the through via in a first region of the substrate and a second plurality of scallops adjacent the through via in a second region of the substrate, each of the scallops of the first plurality of scallops having a first depth, each of the scallops of the second plurality of scallops having a second depth, the first depth being greater than the second depth.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsu-Lun Liu, Wen-Hsiung Lu, Ming-Da Cheng, Chen-En Yen, Cheng-Lung Yang, Kuanchih Huang
  • Patent number: 11769716
    Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes at least one substrate and an interconnection structure. The at least one substrate has a cavity partially defined by an inner sidewall of the at least one substrate and a channel disposed at a bottom of the at least one substrate. The channel laterally penetrates through the at least one substrate. The interconnections structure is disposed over the substrate, and the interconnection structure has a through hole penetrating through the interconnection structure. The through hole, the cavity and the channel are in spatial communication with each other.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Sheng Lin, Cheng-Lung Yang, Chin-Yu Ku, Ming-Da Cheng, Wen-Hsiung Lu, Tang-Wei Huang, Fu Wei Liu
  • Publication number: 20220310492
    Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes at least one substrate and an interconnection structure. The at least one substrate has a cavity partially defined by an inner sidewall of the at least one substrate and a channel disposed at a bottom of the at least one substrate. The channel laterally penetrates through the at least one substrate. The interconnections structure is disposed over the substrate, and the interconnection structure has a through hole penetrating through the interconnection structure. The through hole, the cavity and the channel are in spatial communication with each other.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Sheng Lin, Cheng-Lung Yang, Chin-Yu Ku, Ming-Da Cheng, Wen-Hsiung Lu, Tang-Wei Huang, Fu Wei Liu
  • Publication number: 20220293494
    Abstract: A method of forming a semiconductor device includes following steps. A first organic layer is formed to cover a first conductive layer. A first opening is formed in the first organic layer to expose a first surface of the first conductive layer. A first silicon layer is formed on a sidewall of the first opening and the first surface of the first conductive layer. A first dielectric layer is formed on the sidewall of the first opening and the first surface of the first conductive layer over the first silicon layer. By using a first mask, portions of the first silicon layer and the first dielectric layer on the first surface are simultaneously removed to expose the first surface, wherein after removing the portions of the first silicon layer and the first dielectric layer, the first dielectric layer covers a top surface of the first silicon layer.
    Type: Application
    Filed: May 30, 2022
    Publication date: September 15, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lung Yang, Chih-Hung Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
  • Patent number: 11387168
    Abstract: A semiconductor device includes a first conductive layer, an organic layer and a silicon layer. The first conductive layer includes a first surface. The organic layer is disposed over the first surface of the first conductive layer. The silicon layer is disposed over the organic layer and extended onto and in contact with the first surface of the first conductive layer.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lung Yang, Chih-Hung Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
  • Publication number: 20220216133
    Abstract: A through via comprising sidewalls having first scallops in a first region and second scallops in a second region and a method of forming the same are disclosed. In an embodiment, a semiconductor device includes a first substrate; and a through via extending through the substrate, the substrate including a first plurality of scallops adjacent the through via in a first region of the substrate and a second plurality of scallops adjacent the through via in a second region of the substrate, each of the scallops of the first plurality of scallops having a first depth, each of the scallops of the second plurality of scallops having a second depth, the first depth being greater than the second depth.
    Type: Application
    Filed: March 25, 2022
    Publication date: July 7, 2022
    Inventors: Hsu-Lun Liu, Wen-Hsiung Lu, Ming-Da Cheng, Chen-En Yen, Cheng-Lung Yang, Kuanchih Huang
  • Patent number: 11289404
    Abstract: A through via comprising sidewalls having first scallops in a first region and second scallops in a second region and a method of forming the same are disclosed. In an embodiment, a semiconductor device includes a first substrate; and a through via extending through the substrate, the substrate including a first plurality of scallops adjacent the through via in a first region of the substrate and a second plurality of scallops adjacent the through via in a second region of the substrate, each of the scallops of the first plurality of scallops having a first depth, each of the scallops of the second plurality of scallops having a second depth, the first depth being greater than the second depth.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsu-Lun Liu, Wen-Hsiung Lu, Ming-Da Cheng, Chen-En Yen, Cheng-Lung Yang, Kuanchih Huang
  • Patent number: 11127703
    Abstract: Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Yu Ku, Cheng-Lung Yang, Chen-Shien Chen, Hon-Lin Huang, Chao-Yi Wang, Ching-Hui Chen, Chien-Hung Kuo
  • Publication number: 20210225735
    Abstract: A through via comprising sidewalls having first scallops in a first region and second scallops in a second region and a method of forming the same are disclosed. In an embodiment, a semiconductor device includes a first substrate; and a through via extending through the substrate, the substrate including a first plurality of scallops adjacent the through via in a first region of the substrate and a second plurality of scallops adjacent the through via in a second region of the substrate, each of the scallops of the first plurality of scallops having a first depth, each of the scallops of the second plurality of scallops having a second depth, the first depth being greater than the second depth.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Inventors: Hsu-Lun Liu, Wen-Hsiung Lu, Ming-Da Cheng, Chen-En Yen, Cheng-Lung Yang, Kuanchih Huang
  • Publication number: 20200343162
    Abstract: A semiconductor device includes a first conductive layer, an organic layer and a silicon layer. The first conductive layer includes a first surface. The organic layer is disposed over the first surface of the first conductive layer. The silicon layer is disposed over the organic layer and extended onto and in contact with the first surface of the first conductive layer.
    Type: Application
    Filed: July 9, 2020
    Publication date: October 29, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Lung Yang, Chih-Hung Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
  • Patent number: 10741477
    Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor devices includes a first conductive layer, an organic layer, a silicon layer, a magnetic layer and a second conductive layer. The organic layer is disposed over and exposes a portion of the first conductive layer. The silicon layer is disposed on and in contact with the organic layer. The magnetic layer is disposed over the first conductive layer. The second conductive layer is disposed over the organic layer and the magnetic layer to electrically connect the first conductive layer.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Lung Yang, Chih-Hung Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
  • Publication number: 20190295925
    Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor devices includes a first conductive layer, an organic layer, a silicon layer, a magnetic layer and a second conductive layer. The organic layer is disposed over and exposes a portion of the first conductive layer. The silicon layer is disposed on and in contact with the organic layer. The magnetic layer is disposed over the first conductive layer. The second conductive layer is disposed over the organic layer and the magnetic layer to electrically connect the first conductive layer.
    Type: Application
    Filed: March 23, 2018
    Publication date: September 26, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Lung Yang, CHIH-HUNG Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
  • Publication number: 20190229081
    Abstract: Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Yu Ku, Cheng-Lung Yang, Chen-Shien Chen, Hon-Lin Huang, Chao-Yi Wang, Ching-Hui Chen, Chien-Hung Kuo
  • Patent number: 10276528
    Abstract: A semiconductor device and a manufacturing method for the semiconductor device are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump a spacer and surrounds the bump and disposed between the etching stop layer and the bump.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Yu Ku, Cheng-Lung Yang, Chen-Shien Chen, Hon-Lin Huang, Chao-Yi Wang, Ching-Hui Chen, Chien-Hung Kuo
  • Publication number: 20190027452
    Abstract: A semiconductor device and a manufacturing method for the semiconductor device are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump a spacer and surrounds the bump and disposed between the etching stop layer and the bump.
    Type: Application
    Filed: July 18, 2017
    Publication date: January 24, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Yu Ku, Cheng-Lung Yang, Chen-Shien Chen, Hon-Lin Huang, Chao-Yi Wang, Ching-Hui Chen, Chien-Hung Kuo
  • Patent number: 6541399
    Abstract: A new method is provided of measuring actual temperatures across the surface of a semiconductor wafer. The thickness of a layer of Sub-Atmospheric TEOS Undoped Silicon Glass (SAUSG) is used to monitor the temperature distribution across the surface of a silicon substrate.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: April 1, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Mong-Chi Hung, Pin-Huan Wu, Cheng-Lung Yang