Abstract: A circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor has a first end and a second end. The second transistor has a first end and a second end, wherein the first end of the second transistor is coupled to the first end of the first transistor. The third transistor has a first end and a second end, wherein the second end of the third transistor is coupled to the second end of the second transistor. The fourth transistor has a first end coupled to the second end of the first transistor. The fourth transistor has a bottom gate and an oxide semiconductor layer, and the second transistor has a top gate and a silicon semiconductor layer.

Abstract: First fire operations for an ovonic threshold switch (OTS) selector is provided. A first fire operation includes setting a peak amplitude of a voltage pulse, and performing at least one cycle, including: providing the voltage pulse to the OTS selector; sensing an output current passing through the OTS selector in response to the received voltage pulse; comparing a peak amplitude of the voltage pulse with a maximum peak amplitude ensuring initialization of the OTS selector; ending the first fire operation if the peak amplitude reaches the maximum peak amplitude; comparing the output current with a target current indicative of initialization of the OTS selector if the peak amplitude is lower than the maximum peak amplitude; ending the first fire operation if the output current reaches the target current; and setting another voltage pulse with a greater peak amplitude if the output current is lower than the target current.

Abstract: A memory device includes a substrate, a transistor disposed over the substrate, an interconnect structure disposed over and electrically connected to the transistor, and a memory stack disposed between two adjacent metallization layers of the interconnect structure. The memory stack includes a bottom electrode disposed over the substrate and electrically connected to a bit line, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer and electrically connected to a word line. Besides, at least one moisture-resistant layer is provided adjacent to and in physical contact with the selector layer, and the at least one moisture-resistant layer includes an amorphous material.

Abstract: A driver circuit which includes an output circuit and a control circuit coupled to the output circuit. The driver circuit includes a pull-up transistor with a silicon semiconductor layer. The control circuit includes a first transistor with an oxide semiconductor layer.

Abstract: An electronic device is provided with an active area and a peripheral area, and includes a first substrate, a second substrate, a sealant frame, a conductive member and a wall structure. The second substrate is arranged opposite to the first substrate. The sealant frame is arranged on the first substrate and surrounds the active area. The conductive member is arranged on the peripheral area, wherein part of the conductive member is arranged between the first substrate and the second substrate. The wall structure is arranged between the first substrate and the second substrate, wherein the wall structure is arranged between the sealant frame and the conductive member when viewed in a top view direction.

Abstract: A driver circuit which includes an output circuit and a control circuit coupled to the output circuit. The driver circuit includes a pull-up transistor with a silicon semiconductor layer. The control circuit includes a first transistor with an oxide semiconductor layer.

Abstract: A driver circuit which includes an output circuit and a control circuit coupled to the output circuit. The driver circuit includes a pull-up transistor with a silicon semiconductor layer. The control circuit includes a first transistor with an oxide semiconductor layer.

Abstract: A display device includes a pixel array, multiple data lines, and multiple gate lines. The pixel array includes multiple pixel units. The data lines are coupled to the pixel array. The gate lines are coupled to the pixel array. One of the pixel units includes a switch circuit, a display unit, and a first voltage level shifting circuit. The switch circuit is coupled to one of the data lines and one of the gate lines. The first voltage level shifting circuit is coupled between the switch circuit and the display unit and configured to adjust the voltage level of a data driving signal provided by the data line to the display unit.

Abstract: A touch device including an array substrate, at least one gate driving circuit, an opposite substrate and a shielding pattern is provided. The array substrate has a display region and a peripheral region connecting to the display region. The gate driving circuit is disposed on the array substrate and located in the peripheral region. The opposite substrate is disposed opposite to the array substrate. The shielding pattern is disposed between the array substrate and the opposite substrate. The shielding pattern projected on the array substrate is formed a first projection, the gate driving circuit projected on the array substrate is formed a second projection, the first projection at least partially overlaps with the second projection.

Abstract: A driver circuit which includes an output circuit and a control circuit coupled to the output circuit. The driver circuit includes a pull-up transistor with a silicon semiconductor layer. The control circuit includes a first transistor with an oxide semiconductor layer.

Abstract: A driver circuit which includes an output circuit and a control circuit coupled to the output circuit. The driver circuit includes a pull-up transistor with a silicon semiconductor layer. The control circuit includes a first transistor with an oxide semiconductor layer.

Abstract: A touch device including an array substrate, at least one gate driving circuit, an opposite substrate and a shielding pattern is provided. The array substrate has a display region and a peripheral region connecting to the display region. The gate driving circuit is disposed on the array substrate and located in the peripheral region. The opposite substrate is disposed opposite to the array substrate. The shielding pattern is disposed between the array substrate and the opposite substrate. The shielding pattern projected on the array substrate is formed a first projection, the gate driving circuit projected on the array substrate is formed a second projection, the first projection at least partially overlaps with the second projection.

Abstract: A display device includes a pixel array, multiple data lines, and multiple gate lines. The pixel array includes multiple pixel units. The data lines are coupled to the pixel array. The gate lines are coupled to the pixel array. One of the pixel units includes a switch circuit, a display unit, and a first voltage level shifting circuit. The switch circuit is coupled to one of the data lines and one of the gate lines. The first voltage level shifting circuit is coupled between the switch circuit and the display unit and configured to adjust the voltage level of a data driving signal provided by the data line to the display unit.

Abstract: A touch device including an array substrate, at least one gate driving circuit, an opposite substrate and a shielding pattern is provided. The array substrate has a display region and a peripheral region connecting to the display region. The gate driving circuit is disposed on the array substrate and located in the peripheral region. The opposite substrate is disposed opposite to the array substrate. The shielding pattern is disposed between the array substrate and the opposite substrate. The shielding pattern projected on the array substrate is formed a first projection, the gate driving circuit projected on the array substrate is formed a second projection, the first projection at least partially overlaps with the second projection.

Abstract: A display device includes an array substrate having a first data line along a first direction. The array substrate further includes a first insulating layer and a common electrode. The insulating layer disposes on the first data line. The common electrode disposes on the insulating layer and includes a plurality of sub-common electrode rows disposed along the second direction which is different from the first direction. The sub-common electrode rows extend along the second direction. The sub-common electrode rows include a first portion, a second portion separated from the first portion, and a connection portion connecting the first and second portions. The first data line overlapping the sub-common electrode rows, and the number of first portions overlapping the first data line is greater than the number of connection portions overlapping the first data.

Abstract: A display device is disclosed, which comprises: a first substrate; a second substrate disposed adjacent to the first substrate and partially covering the first substrate, wherein the second substrate comprises a second arc edge and a second side, and the second arc edge connects to the second side; a driving unit disposed on a part of the first substrate uncovered with the second substrate; and a compensation panel disposed on the driving unit and comprising a third arc edge and a third side, wherein the third arc edge connects to the third side, wherein the third side corresponds to the second side, and the third arc edge corresponds to the second arc edge.

Abstract: A display device includes an array substrate having a first data line along a first direction. The array substrate further includes a first insulating layer and a common electrode. The insulating layer disposes on the first data line. The common electrode disposes on the insulating layer and includes a plurality of sub-common electrode rows disposed along the second direction which is different from the first direction. The sub-common electrode rows extend along the second direction. The sub-common electrode rows include a first portion, a second portion separated from the first portion, and a connection portion connecting the first and second portions. The first data line overlapping the sub-common electrode rows, and the number of first portions overlapping the first data line is greater than the number of connection portions overlapping the first data.

Abstract: A transflective type liquid crystal panel includes a plurality of sub-pixels arranged in rows and columns to form a sub-pixel array, a plurality of first wires extending along the row direction or the column direction, and a plurality of second wires which are parallel with the first wires. The plurality of sub-pixels includes transmissive sub-pixels and reflective sub-pixels. Each row and column in the sub-pixel array has both transmissive sub-pixels and reflective sub-pixels. The transmissive sub-pixels are connected to and driven by the first wires, and the reflective sub-pixels are connected to and driven by the second wires.

Abstract: A driver circuit which includes an output circuit and a control circuit coupled to the output circuit. The driver circuit includes a pull-up transistor with a silicon semiconductor layer. The control circuit includes a first transistor with an oxide semiconductor layer.

Abstract: A display panel comprising a substrate, a plurality of gate lines, source lines, semiconductor layers and light shielding layers is provided. The gate lines are disposed on the substrate in parallel. The source lines are disposed on the substrate in parallel. The gate lines and the source lines are intercrossed to define a plurality of pixel areas. The semiconductor layers are disposed on the corresponding pixel areas, and each semiconductor layer includes at least one channel region overlapping each gate line. The slight shielding layers are located between the channel regions and the substrate. In a normal direction of the substrate, one of the gate lines is overlapped by two of the light shielding layers, and one of the light shielding layers overlaps even number of the source lines.