Patents by Inventor Cheng-Mu Lin

Cheng-Mu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEM AND METHOD FOR CORRECTING NON-IDEAL WAFER TOPOGRAPHY
    Publication number: 20220319895
    Abstract: A scanner includes a light source configured to apply a light to a backside of a wafer. The light is reflected from the backside of the wafer. A first mirror is configured to receive the light from the backside of the wafer and reflect the light. A sensor is configured to receive the light from the first mirror and generate an output signal indicative of a backside topography of the wafer.
    Type: Application
    Filed: June 17, 2022
    Publication date: October 6, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Mu LIN, Chi-Hung Liao, Yi-Ming Dai, Yueh Lin Yang
  • System and method for correcting non-ideal wafer topography
    Patent number: 11367644
    Abstract: A scanner includes a light source configured to apply a light to a backside of a wafer. The light is reflected from the backside of the wafer. A first mirror is configured to receive the light from the backside of the wafer and reflect the light. A sensor is configured to receive the light from the first mirror and generate an output signal indicative of a backside topography of the wafer.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: June 21, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Mu Lin, Chi-Hung Liao, Yi-Ming Dai, Yueh Lin Yang
  • SYSTEM AND METHOD FOR CORRECTING NON-IDEAL WAFER TOPOGRAPHY
    Publication number: 20200402828
    Abstract: A scanner includes a light source configured to apply a light to a backside of a wafer. The light is reflected from the backside of the wafer. A first mirror is configured to receive the light from the backside of the wafer and reflect the light. A sensor is configured to receive the light from the first mirror and generate an output signal indicative of a backside topography of the wafer.
    Type: Application
    Filed: September 8, 2020
    Publication date: December 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Mu Lin, Chi-Hung Liao, Yi-Ming Dai, Yueh Lin Yang
  • System and method for correcting non-ideal wafer topography
    Patent number: 10770327
    Abstract: A scanner includes a light source configured to apply a light to a backside of a wafer. The light is reflected from the backside of the wafer. A first mirror is configured to receive the light from the backside of the wafer and reflect the light. A sensor is configured to receive the light from the first mirror and generate an output signal indicative of a backside topography of the wafer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Mu Lin, Chi-Hung Liao, Yi-Ming Dai, Yueh Lin Yang
  • SYSTEM AND METHOD FOR CORRECTING NON-IDEAL WAFER TOPOGRAPHY
    Publication number: 20190035664
    Abstract: A scanner includes a light source configured to apply a light to a backside of a wafer. The light is reflected from the backside of the wafer. A first mirror is configured to receive the light from the backside of the wafer and reflect the light. A sensor is configured to receive the light from the first mirror and generate an output signal indicative of a backside topography of the wafer.
    Type: Application
    Filed: March 30, 2018
    Publication date: January 31, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Mu Lin, Chi-Hung Liao, Yi-Ming Dai, Yueh Lin Yang