Patents by Inventor Cheng Ping Lin
Cheng Ping Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12221536Abstract: A component (A1) thereof includes an epoxy resin having at least one of a naphthalene skeleton or a biphenyl skeleton. A component (A2) thereof includes a phenolic resin having at least one of the naphthalene skeleton or the biphenyl skeleton. A component (B) thereof includes a high molecular weight substance having structures expressed by at least formulae (b2) and (b3) out of formulae (b1), (b2), and (b3) and having a weight average molecular weight equal to or greater than 200,000 and equal to or less than 850,000. A component (C1) thereof includes a first filler obtained by subjecting a first inorganic filler to surface treatment using a first silane coupling agent expressed by formula (c1). A component (C2) thereof includes a second filler obtained by subjecting a second inorganic filler to surface treatment using a second silane coupling agent expressed by formula (c2).Type: GrantFiled: March 25, 2021Date of Patent: February 11, 2025Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Cheng Ping Lin, Toshiyuki Makita, Naohito Fukuya
-
Patent number: 12021037Abstract: Package structures and methods for forming the same are provided. The method includes forming a passivation layer having an opening and forming a first seed layer in the opening. The method further includes filling the opening with a conductive layer over the first seed layer and bonding an integrated circuit die to the conductive layer over a first side of the passivation layer. The method further includes removing a portion of the first seed layer to expose a top surface of the conductive layer and to partially expose a first sidewall of the passivation layer from a second side of the passivation layer and forming a second seed layer over the top surface of the conductive layer and over the first sidewall of the passivation layer.Type: GrantFiled: December 8, 2022Date of Patent: June 25, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Da Tsai, Cheng-Ping Lin, Wei-Hung Lin, Chih-Wei Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
-
Publication number: 20230174772Abstract: A component (A1) thereof includes an epoxy resin having at least one of a naphthalene skeleton or a biphenyl skeleton. A component (A2) thereof includes a phenolic resin having at least one of the naphthalene skeleton or the biphenyl skeleton. A component (B) thereof includes a high molecular weight substance having structures expressed by at least formulae (b2) and (b3) out of formulae (b1), (b2), and (b3) and having a weight average molecular weight equal to or greater than 200,000 and equal to or less than 850,000. A component (C1) thereof includes a first filler obtained by subjecting a first inorganic filler to surface treatment using a first silane coupling agent expressed by formula (c1). A component (C2) thereof includes a second filler obtained by subjecting a second inorganic filler to surface treatment using a second silane coupling agent expressed by formula (c2).Type: ApplicationFiled: March 25, 2021Publication date: June 8, 2023Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventors: Cheng Ping LIN, Toshiyuki MAKITA, Naohito FUKUYA
-
Publication number: 20230098830Abstract: Package structures and methods for forming the same are provided. The method includes forming a passivation layer having an opening and forming a first seed layer in the opening. The method further includes filling the opening with a conductive layer over the first seed layer and bonding an integrated circuit die to the conductive layer over a first side of the passivation layer. The method further includes removing a portion of the first seed layer to expose a top surface of the conductive layer and to partially expose a first sidewall of the passivation layer from a second side of the passivation layer and forming a second seed layer over the top surface of the conductive layer and over the first sidewall of the passivation layer.Type: ApplicationFiled: December 8, 2022Publication date: March 30, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Da TSAI, Cheng-Ping LIN, Wei-Hung LIN, Chih-Wei LIN, Ming-Da CHENG, Ching-Hua HSIEH, Chung-Shi LIU
-
Patent number: 11532564Abstract: Package structures and methods for forming the same are provided. The package structure includes an integrated circuit die and a package layer surrounding the integrated circuit die. The package structure also includes a redistribution structure over the package layer and electrically connected to the integrated circuit die. The redistribution structure includes a passivation layer and a conductive layer formed in the passivation layer. The integrated circuit die further includes a connector formed over the conductive layer and covered a top surface of the passivation layer. In addition, a bottom surface of the connector and a top surface of the connector are both wider than a neck portion of the connector.Type: GrantFiled: December 14, 2020Date of Patent: December 20, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Da Tsai, Cheng-Ping Lin, Wei-Hung Lin, Chih-Wei Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
-
Publication number: 20210098384Abstract: Package structures and methods for forming the same are provided. The package structure includes an integrated circuit die and a package layer surrounding the integrated circuit die. The package structure also includes a redistribution structure over the package layer and electrically connected to the integrated circuit die. The redistribution structure includes a passivation layer and a conductive layer formed in the passivation layer. The integrated circuit die further includes a connector formed over the conductive layer and covered a top surface of the passivation layer. In addition, a bottom surface of the connector and a top surface of the connector are both wider than a neck portion of the connector.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Da TSAI, Cheng-Ping LIN, Wei-Hung LIN, Chih-Wei LIN, Ming-Da CHENG, Ching-Hua HSIEH, Chung-Shi LIU
-
Patent number: 10867932Abstract: Package structures and methods for forming the same are provided. The method includes forming a redistribution structure embedded in a passivation layer over a carrier substrate and bonding an integrated circuit die to the redistribution structure through first connectors. The method further includes removing the carrier substrate to expose a bottom portion of the redistribution structure and removing the bottom portion of the redistribution structure to form an opening in the passivation layer. The method further includes forming a second connector over the redistribution structure. In addition, the second connector includes an extending portion extending into the opening in the passivation layer.Type: GrantFiled: January 13, 2020Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Da Tsai, Cheng-Ping Lin, Wei-Hung Lin, Chih-Wei Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
-
Publication number: 20200152576Abstract: Package structures and methods for forming the same are provided. The method includes forming a redistribution structure embedded in a passivation layer over a carrier substrate and bonding an integrated circuit die to the redistribution structure through first connectors. The method further includes removing the carrier substrate to expose a bottom portion of the redistribution structure and removing the bottom portion of the redistribution structure to form an opening in the passivation layer. The method further includes forming a second connector over the redistribution structure. In addition, the second connector includes an extending portion extending into the opening in the passivation layer.Type: ApplicationFiled: January 13, 2020Publication date: May 14, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Da TSAI, Cheng-Ping LIN, Wei-Hung LIN, Chih-Wei LIN, Ming-Da CHENG, Ching-Hua HSIEH, Chung-Shi LIU
-
Patent number: 10535609Abstract: Package structures and methods for forming the same are provided. A package structure includes a package layer. The package structure also includes an integrated circuit die and a first connector embedded in the package layer. The package structure further includes a redistribution layer over the package layer. The integrated circuit die is electrically connected to the redistribution layer through the first connector. In addition, the package structure includes a passivation layer over the redistribution layer. The package structure also includes a second connector over the passivation layer. A first portion of the redistribution layer and a second portion of the second connector extend into the passivation layer. The second portion of the second connector has a tapered profile along a direction from the integrated circuit die towards the first connector.Type: GrantFiled: June 27, 2018Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Da Tsai, Cheng-Ping Lin, Wei-Hung Lin, Chih-Wei Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
-
Publication number: 20180308800Abstract: Package structures and methods for forming the same are provided. A package structure includes a package layer. The package structure also includes an integrated circuit die and a first connector embedded in the package layer. The package structure further includes a redistribution layer over the package layer. The integrated circuit die is electrically connected to the redistribution layer through the first connector. In addition, the package structure includes a passivation layer over the redistribution layer. The package structure also includes a second connector over the passivation layer. A first portion of the redistribution layer and a second portion of the second connector extend into the passivation layer. The second portion of the second connector has a tapered profile along a direction from the integrated circuit die towards the first connector.Type: ApplicationFiled: June 27, 2018Publication date: October 25, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Da TSAI, Cheng-Ping LIN, Wei-Hung LIN, Chih-Wei LIN, Ming-Da CHENG, Ching-Hua HSIEH, Chung-Shi LIU
-
Patent number: 10014260Abstract: Package structures and methods for forming the same are provided. A method for forming a package structure includes providing a carrier substrate. The method also includes forming a conductive layer over the carrier substrate. The method further includes forming a passivation layer over the conductive layer. The passivation layer includes openings that expose portions of the conductive layer. In addition, the method includes bonding integrated circuit dies to the portions of the conductive layer through bumps. There is a space between the integrated circuit dies and the passivation layer. The method also includes filling the space with a first molding compound. The first molding compound surrounds the bumps and the integrated circuit dies. The method further includes forming a second molding compound capping the first molding compound and the integrated circuit dies. The passivation layer has a sidewall that is covered by the second molding compound.Type: GrantFiled: November 10, 2016Date of Patent: July 3, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Da Tsai, Cheng-Ping Lin, Wei-Hung Lin, Chih-Wei Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
-
Publication number: 20180130749Abstract: Package structures and methods for forming the same are provided. A method for forming a package structure includes providing a carrier substrate. The method also includes forming a conductive layer over the carrier substrate. The method further includes forming a passivation layer over the conductive layer. The passivation layer includes openings that expose portions of the conductive layer. In addition, the method includes bonding integrated circuit dies to the portions of the conductive layer through bumps. There is a space between the integrated circuit dies and the passivation layer. The method also includes filling the space with a first molding compound. The first molding compound surrounds the bumps and the integrated circuit dies. The method further includes forming a second molding compound capping the first molding compound and the integrated circuit dies. The passivation layer has a sidewall that is covered by the second molding compound.Type: ApplicationFiled: November 10, 2016Publication date: May 10, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Da TSAI, Cheng-Ping LIN, Wei-Hung LIN, Chih-Wei LIN, Ming-Da CHENG, Ching-Hua HSIEH, Chung-Shi LIU
-
Patent number: 7612326Abstract: An angle-calculation apparatus for three-phase optical encoder receives three-phase sinusoidal signals 120 degree phase from the optical encoder and obtains angle information for a motor rotor. The angle-calculation apparatus includes an A/D converter, a digital signal processor (DSP), a phase digitalizer and a digital counter. The A/D converter converts three-phase analog signals of the optical encoder into three-phase digital signals. The phase digitalizer converts the three-phase analog signals into digital phase signals. The digital counter generates a counting value based on the digital phase signals. The DSP performs an inverse trigonometric function calculation on a relatively linear region of the three-phase digital signals to obtain the angle information. The DSP obtains the rotation turn number and rotation direction of the motor rotor according to the counting value.Type: GrantFiled: August 27, 2007Date of Patent: November 3, 2009Assignee: Delta Electronics Inc.Inventors: Chin-Shiong Tsai, Cheng-Ping Lin, Meng-Chang Lin, Mi-Tine Tsai, Po-Ming Chen
-
Patent number: 7547875Abstract: A high-precision absolute type encoder apparatus includes a controller electrically connected to an incremental type encoder and generating a control signal to the incremental type encoder, a comparator electrically connected to outputs of the incremental type encoder and generating first pulse signals, a latch unit electrically connected to outputs of the comparator and generating second pulse signals by latching the generating first pulse signals. When power failure occurs, the controller generates the control signal as successive pulses with predetermined period to drive the latch unit and the incremental type encoder. Therefore, the controller knows angular information of the incremental type encoder by counting the second pulse signals. The absolute angular information can be obtained by combining the angular information and an initial position after power failure.Type: GrantFiled: May 29, 2008Date of Patent: June 16, 2009Assignee: Delta Electronics, Inc.Inventors: Chin-Shiong Tsai, Po-Ming Chen, Meng-Chang Lin, Cheng-Ping Lin
-
Publication number: 20090058349Abstract: An angle-calculation apparatus for three-phase optical encoder receives three-phase sinusoidal signals 120 degree phase from the optical encoder and obtains angle information for a motor rotor. The angle-calculation apparatus includes an A/D converter, a digital signal processor (DSP), a phase digitalizer and a digital counter. The A/D converter converts three-phase analog signals of the optical encoder into three-phase digital signals. The phase digitalizer converts the three-phase analog signals into digital phase signals. The digital counter generates a counting value based on the digital phase signals. The DSP performs an inverse trigonometric function calculation on a relatively linear region of the three-phase digital signals to obtain the angle information. The DSP obtains the rotation turn number and rotation direction of the motor rotor according to the counting value.Type: ApplicationFiled: August 27, 2007Publication date: March 5, 2009Inventors: Chin-Shiong TSAI, Cheng-Ping Lin, Meng-Chang Lin, Mi-Tine Tsai, Po-Ming Chen
-
Patent number: 7485833Abstract: A rare earth element contained substrate for heat generating device contains the rare earth elements, compounds of the rare earth elements, or rare earth minerals so as to heighten its withstanding temperature and improve its heat dissipation. The substrate is also able to radiate a far infrared ray and yield negative ions for purifying the air.Type: GrantFiled: July 14, 2005Date of Patent: February 3, 2009Inventor: Cheng Ping Lin
-
Patent number: 7421194Abstract: Disclosed is a quartz heater tube module in which the individual quartz heater tube proper has a first and a second coverings covered on the outer surface of the glass tube. The first covering is provided with a first electrode in electrical connection with an electrode of the quartz heater tube proper; and the second covering is provided with a second electrode in electrical connection with the other electrode of the quartz heater tube proper. In this manner, the quartz heater tube proper is securely protected by the aforesaid two coverings from breaking with an external impact. A plurality of tube propers can be connected in series or parallel by adaptive sleeves so as to form an impact resistant quartz heater tube module.Type: GrantFiled: May 17, 2006Date of Patent: September 2, 2008Inventor: Cheng Ping Lin
-
Patent number: 7415198Abstract: A quartz heater tube consists of a tube body whose two ends being respectively sealed with a plug, and each plug is provided with a built-in electrode. The inner cavity of the tube body is filled with an inertia gas after being evacuated, and the inner surface thereof is coated with a layer of electrical film which being electrically in connection with the two electrodes. By this construction, when the quartz heater tube is in operation, the electrical film is able to avoid oxidation owing to protection of the inertia gas which serves to isolate the electrical film from the outside air thereby prolonging the lifespan of the quartz heater tube.Type: GrantFiled: January 20, 2006Date of Patent: August 19, 2008Inventor: Cheng Ping Lin
-
Patent number: 7386225Abstract: A humidification apparatus, comprising a container and a set of heating tube; wherein water (liquid) can be introduced from a container to one end of said heating tube, and an steam outlet is provided in another end so that the steams generated by heating liquid (water) flowed out or spurted; said heating tube is an electric film where the external surface of the quartz tube is electrified for heating. Steams will be generated when liquid (water) introduced and reserved in the tube is electrified and heated by the electric film and then boiled. Therefore, it is necessary to heat partial liquid depending on the amount of steamed needed, and thus power saving can be achieved.Type: GrantFiled: August 8, 2006Date of Patent: June 10, 2008Inventor: Cheng Ping Lin
-
Publication number: 20080050103Abstract: A humidification apparatus, comprising a container and a set of heating tube; wherein water (liquid) can be introduced from a container to one end of said heating tube, and an steam outlet is provided in another end so that the steams generated by heating liquid (water) flowed out or spurted; said heating tube is an electric film where the external surface of the quartz tube is electrified for heating. Steams will be generated when liquid (water) introduced and reserved in the tube is electrified and heated by the electric film and then boiled. Therefore, it is necessary to heat partial liquid depending on the amount of steamed needed, and thus power saving can be achieved.Type: ApplicationFiled: August 8, 2006Publication date: February 28, 2008Inventor: Cheng Ping Lin