Patents by Inventor Cheng-Pu Chiu
Cheng-Pu Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230395657Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.Type: ApplicationFiled: August 18, 2023Publication date: December 7, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Pu Chiu, Tzung-Ying Lee, Dien-Yang Lu, Chun-Kai Chao, Chun-Mao Chiou
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Patent number: 11764261Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.Type: GrantFiled: February 14, 2022Date of Patent: September 19, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Pu Chiu, Tzung-Ying Lee, Dien-Yang Lu, Chun-Kai Chao, Chun-Mao Chiou
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Publication number: 20230290747Abstract: Embodiments provide metal features which dissipate heat generated from a laser drilling process for exposing dummy pads through a dielectric layer. Because the dummy pads are coupled to the metal features, the metal features act as a heat dissipation feature to pull heat from the dummy pad. As a result, reduction in heat is achieved at the dummy pad during the laser drilling process.Type: ApplicationFiled: May 27, 2022Publication date: September 14, 2023Inventors: Chien-Hung Chen, Cheng-Pu Chiu, Chien-Chen Li, Chien-Li Kuo, Ting-Ting Kuo, Li-Hsien Huang, Yao-Chun Chuang, Jun He
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Patent number: 11569235Abstract: A semiconductor device is provided in the disclosure, including a substrate, multiple parallel fins protruding from the substrate and isolated by trenches, and a device insulating layer on the trenches between two fins, wherein the trench is provided with a central first trench and two second trenches at both sides of the first trench, and a depth of the first trench is deeper than a depth of the second trench, and the device insulating layer is provided with a top plane, a first trench and a second trench, and the fins protrude from the top plane, and the bottom surface of the second trench is lower than the bottom surface of the first trench.Type: GrantFiled: October 21, 2020Date of Patent: January 31, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Yi Wang, Tien-Shan Hsu, Cheng-Pu Chiu, Yao-Jhan Wang
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Publication number: 20220165844Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.Type: ApplicationFiled: February 14, 2022Publication date: May 26, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Pu Chiu, Tzung-Ying Lee, Dien-Yang Lu, Chun-Kai Chao, Chun-Mao Chiou
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Patent number: 11289572Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.Type: GrantFiled: November 23, 2020Date of Patent: March 29, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Pu Chiu, Tzung-Ying Lee, Dien-Yang Lu, Chun-Kai Chao, Chun-Mao Chiou
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Publication number: 20210035977Abstract: A semiconductor device is provided in the disclosure, including a substrate, multiple parallel fins protruding from the substrate and isolated by trenches, and a device insulating layer on the trenches between two fins, wherein the trench is provided with a central first trench and two second trenches at both sides of the first trench, and a depth of the first trench is deeper than a depth of the second trench, and the device insulating layer is provided with a top plane, a first trench and a second trench, and the fins protrude from the top plane, and the bottom surface of the second trench is lower than the bottom surface of the first trench.Type: ApplicationFiled: October 21, 2020Publication date: February 4, 2021Inventors: Chih-Yi Wang, Tien-Shan Hsu, Cheng-Pu Chiu, Yao-Jhan Wang
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Patent number: 10868011Abstract: A semiconductor device is provided in the disclosure, including a substrate, multiple parallel fins protruding from the substrate and isolated by trenches, and a device insulating layer on the trenches between two fins, wherein the trench is provided with a central first trench and two second trenches at both sides of the first trench, and a depth of the first trench is deeper than a depth of the second trench, and the device insulating layer is provided with a top plane, a first trench and a second trench, and the fins protrude from the top plane, and the bottom surface of the second trench is lower than the bottom surface of the first trench.Type: GrantFiled: January 17, 2019Date of Patent: December 15, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Yi Wang, Tien-Shan Hsu, Cheng-Pu Chiu, Yao-Jhan Wang
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Publication number: 20200203344Abstract: A semiconductor device is provided in the disclosure, including a substrate, multiple parallel fins protruding from the substrate and isolated by trenches, and a device insulating layer on the trenches between two fins, wherein the trench is provided with a central first trench and two second trenches at both sides of the first trench, and a depth of the first trench is deeper than a depth of the second trench, and the device insulating layer is provided with a top plane, a first trench and a second trench, and the fins protrude from the top plane, and the bottom surface of the second trench is lower than the bottom surface of the first trench.Type: ApplicationFiled: January 17, 2019Publication date: June 25, 2020Inventors: Chih-Yi Wang, Tien-Shan Hsu, Cheng-Pu Chiu, Yao-Jhan Wang
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Publication number: 20200194589Abstract: A fin field effect transistor structure with particular gate appearance is provided in this disclosure, featuring a fin on a substrate and a gate on the substrate and traversing over the fin, wherein the fin is divided into an upper portion on a top surface of the fin and a lower portion on two sides of the fin, and the lower portion of the gate has protrusions laterally protruding in said first direction at positions abutting to the fin.Type: ApplicationFiled: January 8, 2019Publication date: June 18, 2020Inventors: Chih-Yi Wang, Cheng-Pu Chiu, Huang-Ren Wei, Tien-Shan Hsu, Chi-Sheng Tseng, Yao-Jhan Wang
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Publication number: 20200194058Abstract: The present invention provides a static random access memory (SRAM), the SRAM includes a substrate, a SRAM pattern disposed on the substrate, wherein the SRAM pattern at least includes a first gate structure, a second gate structure and a third gate structure, arranged along a first direction, wherein the second gate structure and the third gate structure are parallel to the first gate structure, and a gap is disposed between the second gate structure and the third gate structure, and wherein the first gate structure is composed of a first elongated structure, a second elongated structure and a curved structure disposed between the first elongated structure and the second elongated structure, and wherein the curved structure is aligned with the gap along a second direction, and an interconnection contact structure disposed between the first gate structure and the second gate structure, and arranged along the first direction.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Inventors: Te-Chang Hsu, Cheng-Pu Chiu, Chun-Jen Huang, Cheng-Yeh Huang, Che-Hsien Lin, Yao-Jhan Wang
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Patent number: 10686079Abstract: A fin field effect transistor structure with particular gate appearance is provided in this disclosure, featuring a fin on a substrate and a gate on the substrate and traversing over the fin, wherein the fin is divided into an upper portion on a top surface of the fin and a lower portion on two sides of the fin, and the lower portion of the gate has protrusions laterally protruding in said first direction at positions abutting to the fin.Type: GrantFiled: January 8, 2019Date of Patent: June 16, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Yi Wang, Cheng-Pu Chiu, Huang-Ren Wei, Tien-Shan Hsu, Chi-Sheng Tseng, Yao-Jhan Wang
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Patent number: 10622245Abstract: A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.Type: GrantFiled: June 16, 2019Date of Patent: April 14, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chi-Ying Hsieh, Chih-Jung Chen, Chien-Hung Chen, Chih-Yueh Li, Cheng-Pu Chiu, Shih-Min Lu, Yung-Sung Lin
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Publication number: 20190378752Abstract: A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.Type: ApplicationFiled: June 16, 2019Publication date: December 12, 2019Inventors: Chi-Ying Hsieh, Chih-Jung Chen, Chien-Hung Chen, Chih-Yueh Li, Cheng-Pu Chiu, Shih-Min Lu, Yung-Sung Lin
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Patent number: 10446682Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.Type: GrantFiled: January 9, 2019Date of Patent: October 15, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chi-Hsuan Cheng, Cheng-Pu Chiu, Yu-Chih Su, Chih-Yi Wang, Chin-Yang Hsieh, Tien-Shan Hsu, Yao-Jhan Wang
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Patent number: 10373861Abstract: A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.Type: GrantFiled: July 3, 2018Date of Patent: August 6, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chi-Ying Hsieh, Chih-Jung Chen, Chien-Hung Chen, Chih-Yueh Li, Cheng-Pu Chiu, Shih-Min Lu, Yung-Sung Lin
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Publication number: 20190148550Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.Type: ApplicationFiled: January 9, 2019Publication date: May 16, 2019Inventors: Chi-Hsuan Cheng, Cheng-Pu Chiu, Yu-Chih Su, Chih-Yi Wang, Chin-Yang Hsieh, Tien-Shan Hsu, Yao-Jhan Wang
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Patent number: 10283415Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.Type: GrantFiled: September 16, 2018Date of Patent: May 7, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Te-Chang Hsu, An-Chi Liu, Nan-Yuan Huang, Yu-Chih Su, Cheng-Pu Chiu, Tien-Shan Hsu, Chih-Yi Wang, Chi-Hsuan Cheng
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Publication number: 20190103492Abstract: A method for forming epitaxial material on base material includes forming a stress cap layer on a base layer of a first semiconductor material. Then, a stress is induced on the base layer, wherein the stress is a tensile stress or a compressive stress. The stress cap layer is removed. An epitaxial layer of a second semiconductor material is formed on the base layer, wherein the second semiconductor material is different from the first semiconductor material.Type: ApplicationFiled: October 2, 2017Publication date: April 4, 2019Applicant: United Microelectronics Corp.Inventors: Cheng-Pu Chiu, Pei-Yu Chen, Shih-Min Lu, Ming-Yueh Tsai, Yung-Sung Lin, Te-Chang Hsu, Chih-Yi Wang, Chi-Hsuan Cheng, Sheng-Chen Chung, Yao-Jhan Wang
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Publication number: 20190080968Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.Type: ApplicationFiled: September 10, 2017Publication date: March 14, 2019Inventors: Chih-Yi Wang, Tien-Shan Hsu, Yu-Chih Su, Chi-Hsuan Cheng, Cheng-Pu Chiu, Te-Chang Hsu, Chin-Yang Hsieh, An-Chi Liu, Kuan-Lin Chen, Yao-Jhan Wang