Patents by Inventor Cheng Seng HSU

Cheng Seng HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210351139
    Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 11, 2021
    Inventors: Chih-Hsiang Tseng, Yu-Feng Chen, Cheng Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Kuo-Ching Hsu, Hong-Seng Shue, Ming-Hong Cha, Chao-Yi Wang, Mirng-Ji Lii
  • Patent number: 10444783
    Abstract: A voltage-to-current circuit employs low leakage manufacturing process transistor(s) to connect at least one non-controlled terminal (e.g. source, drain, or base of MOSFET) and/or control terminal (e.g. gate of MOSFET) of a low power manufacturing process transistor to a predetermined level such as ground level or power supply voltage level when turning off the low power manufacturing process transistor, so as to connect at least two terminals of the low power manufacturing process transistor to the same voltage level, for avoiding or reducing leakage current of the low power manufacturing process transistor when it is turned off.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: October 15, 2019
    Assignee: PixArt Imaging Inc.
    Inventor: Cheng-Seng Hsu
  • Patent number: 10404934
    Abstract: An analog-to-digital signal processing method applied for an image sensor includes: providing a global analog-to-digital converter (ADC) capable of converting analog signals of all pixels of a pixel array into digital signals; providing a column-parallel ADC capable of respectively converting a plurality of analog signals of a plurality of pixels on different columns of the pixel array into a plurality of digital signals by using a plurality of ADC circuits; and, dynamically selecting and switching to enable one of the global ADC and column-parallel ADC to perform analog-to-digital conversion for analog data/signals of pixels on the pixel array.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: September 3, 2019
    Assignee: PixArt Imaging Inc.
    Inventors: Cheng-Seng Hsu, Jui-Te Chiu
  • Patent number: 10067579
    Abstract: An amending circuit includes a comparing unit, a predetermined voltage generating unit, a roller switch, alight emitting unit switch and a controlling unit. A pin of the mouse and the predetermined voltage generating unit are respectively connected to two input terminals of the comparing unit. The controlling unit is coupled to the light emitting unit switch and the roller switch. The controlling unit switches to a motion detecting mode to drive a current of the current source to flow toward a second pin via the first pin and a light emitting unit of the mouse. The controlling unit further switches to a roller detecting mode to set a pressure of the first pin lower than a predetermined voltage of the predetermined voltage generating unit while the roller is grounded or to set the first pin higher than the predetermined voltage while the roller is not grounded.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: September 4, 2018
    Assignee: PixArt Imaging Inc.
    Inventors: Cheng-Seng Hsu, Jui-Te Chiu, Chung-Ting Yang
  • Publication number: 20180175793
    Abstract: A voltage-to-current circuit employs low leakage manufacturing process transistor(s) to connect at least one non-controlled terminal (e.g. source, drain, or base of MOSFET) and/or control terminal (e.g. gate of MOSFET) of a low power manufacturing process transistor to a predetermined level such as ground level or power supply voltage level when turning off the low power manufacturing process transistor, so as to connect at least two terminals of the low power manufacturing process transistor to the same voltage level, for avoiding or reducing leakage current of the low power manufacturing process transistor when it is turned off.
    Type: Application
    Filed: May 16, 2017
    Publication date: June 21, 2018
    Inventor: Cheng-Seng Hsu
  • Publication number: 20180103224
    Abstract: An analog-to-digital signal processing method applied for an image sensor includes: providing a global analog-to-digital converter (ADC) capable of converting analog signals of all pixels of a pixel array into digital signals; providing a column-parallel ADC capable of respectively converting a plurality of analog signals of a plurality of pixels on different columns of the pixel array into a plurality of digital signals by using a plurality of ADC circuits; and, dynamically selecting and switching to enable one of the global ADC and column-parallel ADC to perform analog-to-digital conversion for analog data/signals of pixels on the pixel array.
    Type: Application
    Filed: February 15, 2017
    Publication date: April 12, 2018
    Inventors: Cheng-Seng Hsu, Jui-Te Chiu
  • Patent number: 9455823
    Abstract: A four-phase clock generator with timing sequence self-detection including a phase-locked loop (PLL), a frequency dividing module, and a detection and control module. The PLL generates a first to a fourth reference clock signal with the same frequency, respectively, wherein each consecutive two of the first to the fourth reference clock signals have a 90-degree phase difference. The frequency dividing module is coupled to the PLL and determines whether to perform frequency dividing on the first to the fourth reference clock signals to obtain a first through a fourth output clock signal according to a first control signal. The detection and control module is coupled to the frequency dividing module and detects a timing sequence of the first to the fourth output clock signals to output the first control signal accordingly.
    Type: Grant
    Filed: May 25, 2015
    Date of Patent: September 27, 2016
    Assignee: PIXART IMAGING INC.
    Inventor: Cheng-Seng Hsu
  • Publication number: 20160248578
    Abstract: A four-phase clock generator with timing sequence self-detection including a phase-locked loop (PLL), a frequency dividing module, and a detection and control module. The PLL generates a first to a fourth reference clock signal with the same frequency, respectively, wherein each consecutive two of the first to the fourth reference clock signals have a 90-degree phase difference. The frequency dividing module is coupled to the PLL and determines whether to perform frequency dividing on the first to the fourth reference clock signals to obtain a first through a fourth output clock signal according to a first control signal. The detection and control module is coupled to the frequency dividing module and detects a timing sequence of the first to the fourth output clock signals to output the first control signal accordingly.
    Type: Application
    Filed: May 25, 2015
    Publication date: August 25, 2016
    Inventor: CHENG-SENG HSU
  • Publication number: 20160124525
    Abstract: An amending circuit includes a comparing unit, a predetermined voltage generating unit, a roller switch, alight emitting unit switch and a controlling unit. A pin of the mouse and the predetermined voltage generating unit are respectively connected to two input terminals of the comparing unit. The controlling unit is coupled to the light emitting unit switch and the roller switch. The controlling unit switches to a motion detecting mode to drive a current of the current source to flow toward a second pin via the first pin and a light emitting unit of the mouse. The controlling unit further switches to a roller detecting mode to set a pressure of the first pin lower than a predetermined voltage of the predetermined voltage generating unit while the roller is grounded or to set the first pin higher than the predetermined voltage while the roller is not grounded.
    Type: Application
    Filed: October 8, 2015
    Publication date: May 5, 2016
    Inventors: Cheng-Seng Hsu, Jui-Te Chiu, Chung-Ting Yang
  • Patent number: 9325303
    Abstract: The present disclosure illustrates a button detecting circuit and method thereof. The button detecting circuit includes a determining circuit, a voltage selector and a button module. The voltage selector is electrically connected to the determining circuit. The voltage selector has a plurality of candidate voltages arranged in sequence based on magnitudes of the candidate voltages. The button module which is electrically connected to the determining circuit via a single one pin comprises a threshold unit and a button network. The determining circuit receives the candidate voltage outputted from the voltage selector and outputs the candidate voltage to the button module for testing whether the threshold unit will be conducted to find a threshold voltage. The button module generates a scanning current based upon the threshold voltage. The determining circuit senses the scanning current and determines which one of a plurality of buttons disposed in the button network is pressed.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: April 26, 2016
    Assignee: PIXART IMAGING INC.
    Inventors: Cheng Seng Hsu, Jui Te Chiu
  • Publication number: 20160065197
    Abstract: The present disclosure illustrates a button detecting circuit and method thereof. The button detecting circuit includes a determining circuit, a voltage selector and a button module. The voltage selector is electrically connected to the determining circuit. The voltage selector has a plurality of candidate voltages arranged in sequence based on magnitudes of the candidate voltages. The button module which is electrically connected to the determining circuit via a single one pin comprises a threshold unit and a button network. The determining circuit receives the candidate voltage outputted from the voltage selector and outputs the candidate voltage to the button module for testing whether the threshold unit will be conducted to find a threshold voltage. The button module generates a scanning current based upon the threshold voltage. The determining circuit senses the scanning current and determines which one of a plurality of buttons disposed in the button network is pressed.
    Type: Application
    Filed: March 5, 2015
    Publication date: March 3, 2016
    Inventors: Cheng Seng HSU, Jui Te CHIU