Abstract: The present disclosure provides a method for photo-curing 4D printing of a multi-layer structure with an adjustable shape recovery speed, and a multi-layer structure printed thereby. The multi-layer structure printed by the method for photo-curing 4D printing of the multi-layer structure with the adjustable shape recovery speed includes a plurality of deformation units sequentially connected in series, and each of the plurality of the deformation units includes two slow layers, a fast layer, and a transition layer; and the fast layer is arranged between the two slow layers, and the transition layer is arranged between at least one of the two slow layers and the fast layer. In the present disclosure, a low cross-linking layer is doped with a nanocarbon light-absorbing material to solve the problem that the low cross-linking layer is prone to over-curing when a high cross-linking layer is printed on the low cross-linking layer.

Abstract: A water quality detection device including a detection tank, a sensor, the cleaner and a processor is provided. The sensor is disposed on the detection tank and is configured to sense a to-be-detected liquid within the detection tank. The cleaner is configured to clean the sensor. The processor is electrically connected to the sensor and the cleaner and is configured to: execute an initialization procedure, which includes driving the sensor to sense the to-be-detected liquid to obtain a number of initial sensing values and calculating a threshold value according to the initial sensing values; drive the sensor to sense the to-be-detected liquid to obtain a sensing value of the to-be-detected liquid, and determine whether the sensing value of the to-be-detected liquid reaches the threshold value; drive the cleaner to operate when the sensing value of the to-be-detected liquid reaches the threshold value.

Abstract: Aspects of the disclosure provide an evolutionary neural architecture search (ENAS) method. For example, the ENAS method can include steps (a) performing one or more evolutionary operations on an initial population of neural architectures to generate offspring neural architectures, (b) evaluating performance of each of the offspring neural architectures to obtain at least one evaluation value of the offspring neural architecture with respect to a performance metric, (c) adjusting the evaluation values of the offspring neural architectures based on at least one constraint on the evaluation values, (d) selecting at least one of the offspring neural architectures as a new population of neural architectures, and (e) outputting the new population of neural architectures as a last population of neural architectures when a stopping criterion is achieved, or (f) iterating steps (a) to (d) with the new population of neural architectures being taken as the initial population of neural architectures.

Abstract: The disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a package structure, a circuit structure, a bonding structure and an external element. The circuit structure is disposed on the package structure and is electrically connected to the package structure. The circuit structure has a recess. The bonding structure includes a first bonding pad and a second bonding pad. The second bonding pad is disposed in the recess, and the second bonding pad is disposed on the first bonding pad. The bonding structure is disposed between the circuit structure and the external element. The external element is electrically connected to the circuit structure through the bonding structure. A width of the first bonding pad is smaller than a width of the second bonding pad.

Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.

Abstract: This application relates to a negative electrode plate, a secondary battery and apparatus thereof. The secondary battery of the present application comprises a negative electrode plate, the negative electrode plate comprises a composite current collector and a negative electrode active material layer disposed on at least one surface of the composite current collector, the negative electrode active material layer comprises a silicon-based active material, the silicon-based active material accounts for 0.5 wt % to 50 wt % of total mass of the negative electrode active material layer, and the composite current collector comprises a polymer support layer and a metal conductive layer disposed on at least one surface of the polymer support layer. The secondary battery and the negative electrode plate achieve good coordination between the current collector and the negative electrode active material layer.

Abstract: A vinyl-containing copolymer is copolymerized from (a) first compound, (b) second compound, and (c) third compound. (a) First compound is an aromatic compound having a single vinyl group. (b) Second compound is polybutadiene or polybutadiene-styrene having side vinyl groups. (c) Third compound is an acrylate compound. The vinyl-containing copolymer includes 0.003 mol/g to 0.010 mol/g of benzene ring, 0.0005 mol/g to 0.008 mol/g of vinyl group, and 1.2*10?5 mol/g to 2.4*10?4 mol/g of ester group.

Abstract: A plating system and a method thereof are disclosed. The plating system performs a N-stage plating drilling filling process in which a M-th stage plating drilling filling process with a M-th current density is performed on a hole of a substrate for a M-th plating time to form a M-th plating layer on the to-be-plated layer, wherein N is a positive integer equal to or greater than 3, and M is a positive integer positive integer in a range of 1 to N. Therefore, the technical effect of providing a higher drilling filling rate than conventional plating filling technology under a condition that a total thickness of plating layers is fixed can be achieved.

Abstract: A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.

Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.

Abstract: An optoelectronic package structure and a method of manufacturing an optoelectronic package structure are provided. The optoelectronic package structure includes a photonic component. The photonic component has an electrical connection region, a blocking region and a region for accommodating a device. The blocking region is located between the electrical connection region and the region for accommodating a device.

Abstract: A method for manufacturing a package structure includes providing a carrier board; providing at least one die having a top surface, a bottom surface, and a side surface on the carrier board; and forming a protective layer to cover at least a portion of the side surface of the die. The die includes a substrate, a semiconductor layer, a gate structure, a source structure and a drain structure, at least one dielectric layer, and at least one pad. The semiconductor layer is disposed on the substrate. The gate structure is disposed on the semiconductor layer. The source and the drain structures are disposed on opposite sides of the gate structure. The dielectric layer covers the gate, source, and drain structures. The pad is disposed on the dielectric layer and penetrates through the dielectric layer to electrically contact with the gate, source or drain structure.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.

Abstract: A projection device including a light source module, an optical engine module and a projection lens is provided. The optical engine module includes a casing, a heat-conducting base, a heat pipe, a light valve and a thermal conductive layer. The casing has an opening. The heat-conducting base has an assembly opening, wherein the heat-conducting base is disposed on the casing, and the assembly opening is aligned with the opening of the casing. The heat pipe is connected to the heat-conducting base and disposed on the heat-conducting base. The light valve is disposed on the heat-conducting base corresponding to the assembly opening. The light valve is thermally coupled to the heat-conducting base through the thermal conductive layer. The light valve has a first stepped surface and a second stepped surface, and the thermal conductive layer covers at least a part of the first stepped surface and the second stepped surface.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: Aspects of the present disclosure provide a method for training a predictor that predicts performance of a plurality of machine learning (ML) models on platforms. For example, the method can include converting each of the ML models into a plurality of instructions or the instructions and a plurality of intermediate representations (IRs). The method can also include simulating execution of the instructions corresponding to each of the ML models on a platform and generating instruction performance reports. Each of the instruction performance reports can be associated with performance of the instructions corresponding to one of the ML models that are executed on the platform. The method can also include training the predictor with the instructions or the IRs as learning features and the instruction performance reports as learning labels, compiling the predictor into a library file, and storing the library file in a storage device.

Abstract: A three-dimensional sensing system includes a plurality of scanners each emitting a light signal to a scene to be sensed and receiving a reflected light signal, according to which depth information is obtained. Only one scanner executes transmitting corresponding light signal and receiving corresponding reflected light signal at a time.

Abstract: This application discloses a communication method and a related apparatus, and relates to the field of communication technologies. The method is applied to an SD-WAN overlay network. A CPE autonomously generates an SD-WAN overlay routing table, so that communication reliability and flexibility are improved. An RR specifies an overlay multicast RPF route to the CPE to implement SD-WAN overlay multicast communication, and the CPE does not need to perform path computation autonomously, so that a computing power requirement of the CPE is reduced. An identifier of the CPE and an identifier of a site are carried in a multicast join message to implement the SD-WAN overlay multicast communication. A standard IP header is carried in a multicast service packet to implement the SD-WAN overlay multicast communication, so that generalization, applicability, and compatibility are improved.

Abstract: Embodiments of this application disclose a tunnel establishment method. A first communication apparatus may receive first adjacency topology information sent by a second communication apparatus, and establish a first tunnel between the first communication apparatus and the second communication apparatus when the first adjacency topology information matches second adjacency topology information of the first communication apparatus. It can be learned that, in this solution, the first communication apparatus may locally store only the second adjacency topology information of the first communication apparatus. Compared with the conventional technology in which information about two endpoints of a tunnel needs to be configured on the first communication apparatus, configuration for the first communication apparatus is simpler.