Abstract: A liquid crystal display (LCD) of the chiral polymer stabilized alignment (C-PSA) mode, a method of its production and its use as an energy-saving display.

Abstract: An imaging lens system includes seven lens elements which are, in order from an object side to an image side along an optical path, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. Each of the seven lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The first lens element has negative refractive power. The image-side surface of the fifth lens element is convex in a paraxial region thereof. The sixth lens element has negative refractive power. The object-side surface of the sixth lens element is concave in a paraxial region thereof. At least one of the object-side surface and the image-side surface of at least one of the seven lens elements has at least one inflection point.

Abstract: An electric power tool includes a motor, a lifter, a firing pin, an electromagnet, a driving circuit, a latch, and a controller. The lifter is driven by the motor to drive the firing pin to perform a firing action. The driving circuit provides electric current to excite the electromagnet. The latch is moved by the electromagnet from a blocking position where the latch blocks the firing pin to move in a firing direction to a non-blocking position where the latch does not block the firing pin when the electromagnet is in an excited state. The controller, during an excitement period, controls the driving circuit to provide constant current for a first time period to excite the electromagnet to the excited state, and provide pulsating current for a second time period to keep the electromagnet in the excited state.

Abstract: An image quality evaluation system includes an image calibration device, an image capturing device, and a processing device. The image calibration device is placed in a scene and used for displaying a calibration pattern. The capturing device captures a first comparison image of the scene and the calibration pattern. The processing device is configured to obtain the first comparison image and a reference image containing the calibration pattern and compare the calibration pattern in the first comparison image and the reference image to generate calibration information. After being calibrated according to the calibration information, the image capturing device captures a second comparison image of the scene and the calibration pattern, and the processing device compares the calibration pattern in the second comparison image and the reference image to generate an image quality evaluation result.

Abstract: A method for preparing a long-chain branched polypropylene includes subjecting a T-reagent to a polymerization reaction with propylene in the presence of a catalyst composition. The catalyst composition includes an alkylaluminoxane and a metallocene-based catalyst. The metallocene-based catalyst contains a metal selected from the group consisting of titanium (Ti), zirconium (Zr), and hafnium (Hf). The T-reagent having an alkenyl silyl functional group is selected from the group consisting of 1,2-bis[dimethyl(vinyl)silyl]ethane, dimethyldivinylsilane, 7-octenyldimethyl(vinyl)silane, 7-octenyldimethyl(allyl)silane, 4-(but-3-enyl)phenyldimethyl(vinyl)silane, 4-(but-3-enyl)phenyldimethyl(allyl)silane, and combinations thereof.

Abstract: A multi-spray RRC process with dynamic control to improve final yield and further reduce resist cost is disclosed. In one embodiment, a method, includes: dispensing a first layer of solvent on a semiconductor substrate while spinning at a first speed for a first time period; dispensing the solvent on the semiconductor substrate while spinning at a second speed for a second time period so as to transform the first layer to a second layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a third speed for a third time period so as to transform the second layer to a third layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a fourth speed for a fourth time period so as to transform the third layer to a fourth layer of the solvent; and dispensing a first layer of photoresist on the fourth layer of the solvent while spinning at a fifth speed for a fifth period of time.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.

Abstract: An electronic device includes a first metal layer, a first insulating layer disposed on the first metal layer, a second metal layer, a second insulating layer, a third metal layer, a third insulating layer, a fourth metal layer, a fourth insulating layer and an electronic component. The second metal layer is disposed on the first insulating layer. The second insulating layer is disposed on the second metal layer. The third metal layer is disposed on the second insulating layer. The third insulating layer is disposed on the third metal layer. The fourth metal layer is disposed on the third insulating layer. The fourth insulating layer is disposed on the fourth metal layer. The electronic component is disposed on the fourth insulating layer and electrically connected to the fourth metal layer. A Young's modulus of the third insulating layer is less than a Young's modulus of the first insulating layer.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: A semiconductor device includes: a substrate; a seed layer disposed on the substrate; a compound semiconductor stack layer disposed on the seed layer; and a source metal layer and a drain metal layer disposed on the compound semiconductor stack layer. The semiconductor device further includes a conductive layer at least partially covering the source metal layer and the drain metal layer, and covering opposing side surfaces of the seed layer and opposing side surfaces of the compound semiconductor stack layer. The conductive layer electrically connects the seed layer and the source metal layer.

Abstract: A UEFI variable storage system includes a UEFI variable services subsystem coupled to UEFI variable sources, a trusted UEFI variable storage subsystem, and an untrusted UEFI variable storage subsystem. If the UEFI variable services subsystem receives a first UEFI variable during a first UEFI initialization process from a first UEFI variable source and determines that the first UEFI initialization process has not reached an untrusted UEFI variable source point, it stores the first UEFI variable in the trusted UEFI variable storage subsystem. If the UEFI variable services subsystem receives a second UEFI variable during the first UEFI initialization process from a second UEFI variable source and determines that the first UEFI initialization process has reached the untrusted UEFI variable source point, it stores the second UEFI variable in the untrusted UEFI variable storage subsystem.

Abstract: A BIOS module provisioning sequence verification system includes a BIOS subsystem coupled to a TPM and a BIOS storage system including a plurality of firmware volumes. The BIOS subsystem provides a plurality of BIOS modules in a BIOS module provisioning sequence using the plurality of firmware volumes and, for each of the plurality of BIOS modules when that BIOS module is provided during the BIOS module provisioning sequence: retrieves a BIOS module identifier associated with that BIOS module, and updates BIOS module provisioning sequence information using that BIOS module identifier. Following the provisioning of the BIOS modules in the BIOS module provisioning sequence, the BIOS subsystem provides the BIOS module provisioning sequence information to the TPM, with the BIOS module provisioning sequence information configured to be compared to BIOS module provisioning sequence verification information to verify the BIOS module provisioning sequence.

Abstract: Disclosed is a high-voltage device with ESD robustness. The high-voltage device is formed on a surface of a semiconductor substrate of a first type. A deep well of a second type opposite to the first type is formed on the surface. A filed isolation layer on the surface separates a drain active region from a source active region, and a control gate on top of the field isolation layer serves as a gate electrode of the high-voltage device. A first well of the second type at least partially overlaps the source active region, extends below the field isolation layer and at least partially overlaps the control gate. A buried layer of the first type at a bottom of the deep well has an extensive portion below the control gate. The deep well provides a conductive channel allowing current to flow from the drain active region to the source active region.

Abstract: This application provides a packet processing method, a network device, and a network system, and pertains to the field of communication technologies. In the method provided in this application, an intermediate node updates a source IP address of a packet based on an IP address that belongs to a local end in an endpoint IP address of a connection, and updates a destination IP address of the packet based on an IP address that belongs to a remote end in the endpoint IP address of the connection. Therefore, in a scenario in which an SR path crosses underlay transport networks in a plurality of different routing domains, a problem that a packet is discarded because a source IP address is always an IP address of a head end and URPF check fails is avoided.

Abstract: Aspects of the disclosure provide an evolutionary neural architecture search (ENAS) method. For example, the ENAS method can include steps (a) performing one or more evolutionary operations on an initial population of neural architectures to generate offspring neural architectures, (b) evaluating performance of each of the offspring neural architectures to obtain at least one evaluation value of the offspring neural architecture with respect to a performance metric, (c) adjusting the evaluation values of the offspring neural architectures based on at least one constraint on the evaluation values, (d) selecting at least one of the offspring neural architectures as a new population of neural architectures, and (e) outputting the new population of neural architectures as a last population of neural architectures when a stopping criterion is achieved, or (f) iterating steps (a) to (d) with the new population of neural architectures being taken as the initial population of neural architectures.

Abstract: Aspects of the disclosure provide an evolutionary neural architecture search (ENAS) method. For example, the ENAS method can include steps (a) performing one or more evolutionary operations on an initial population of neural architectures to generate offspring neural architectures, (b) evaluating performance of each of the offspring neural architectures to obtain at least one evaluation value of the offspring neural architecture with respect to a performance metric, (c) adjusting the evaluation values of the offspring neural architectures based on at least one constraint on the evaluation values, (d) selecting at least one of the offspring neural architectures as a new population of neural architectures, and (e) outputting the new population of neural architectures as a last population of neural architectures when a stopping criterion is achieved, or (f) iterating steps (a) to (d) with the new population of neural architectures being taken as the initial population of neural architectures.

Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.

Abstract: Aspects of the present disclosure provide a method for training a predictor that predicts performance of a plurality of machine learning (ML) models on platforms. For example, the method can include converting each of the ML models into a plurality of instructions or the instructions and a plurality of intermediate representations (IRs). The method can also include simulating execution of the instructions corresponding to each of the ML models on a platform and generating instruction performance reports. Each of the instruction performance reports can be associated with performance of the instructions corresponding to one of the ML models that are executed on the platform. The method can also include training the predictor with the instructions or the IRs as learning features and the instruction performance reports as learning labels, compiling the predictor into a library file, and storing the library file in a storage device.

Abstract: This application discloses a communication method and a related apparatus, and relates to the field of communication technologies. The method is applied to an SD-WAN overlay network. A CPE autonomously generates an SD-WAN overlay routing table, so that communication reliability and flexibility are improved. An RR specifies an overlay multicast RPF route to the CPE to implement SD-WAN overlay multicast communication, and the CPE does not need to perform path computation autonomously, so that a computing power requirement of the CPE is reduced. An identifier of the CPE and an identifier of a site are carried in a multicast join message to implement the SD-WAN overlay multicast communication. A standard IP header is carried in a multicast service packet to implement the SD-WAN overlay multicast communication, so that generalization, applicability, and compatibility are improved.

Abstract: Embodiments of this application disclose a tunnel establishment method. A first communication apparatus may receive first adjacency topology information sent by a second communication apparatus, and establish a first tunnel between the first communication apparatus and the second communication apparatus when the first adjacency topology information matches second adjacency topology information of the first communication apparatus. It can be learned that, in this solution, the first communication apparatus may locally store only the second adjacency topology information of the first communication apparatus. Compared with the conventional technology in which information about two endpoints of a tunnel needs to be configured on the first communication apparatus, configuration for the first communication apparatus is simpler.