Abstract: An address translation method for use in a system including a plurality of cluster nodes and including the steps of: at a source node, receiving over a first network a communication with a first destination address having an index portion and an offset portion, wherein the index portion includes a partition number portion; providing an address mapping table which maps a plurality of indexes to a corresponding plurality of node ID's, each of the plurality of node ID's identifying a different one of the plurality of cluster nodes; using the index portion from the first destination address as an index into the address mapping table to identify a node ID, wherein the identified node ID identifies a destination node; appending the identified node ID to the first destination address to generate a second destination address; and using the second destination address to send information to a second network of the destination node.

Abstract: A computer system is disclosed which has a plurality of masters, such as a processor, a cache memory or an I/O device controller. Read response time from the main memory is minimized by a read-from-write scheme which gives priority to read commands. If a read command is to access data with the same address of a previously issued but pending write command in the buffer of a memory controller, then the read and write commands are combined and the read/write command is given priority over each other pending read or write command. To further reduce mean read response time, the data to be written to the main memory is transferred directly from the buffer to the master which issued the read command contemporaneously with the execution of the write command on the main memory.

Abstract: An improved memory controller is disclosed for accessing a computer memory, which consists of a plurality of banks of page mode memory cells and is connected to a CPU via a split transaction bus with out-of-order completion capability.