Abstract: A plating system and a method thereof are disclosed. The plating system performs a N-stage plating drilling filling process in which a M-th stage plating drilling filling process with a M-th current density is performed on a hole of a substrate for a M-th plating time to form a M-th plating layer on the to-be-plated layer, wherein N is a positive integer equal to or greater than 3, and M is a positive integer positive integer in a range of 1 to N. Therefore, the technical effect of providing a higher drilling filling rate than conventional plating filling technology under a condition that a total thickness of plating layers is fixed can be achieved.

Abstract: A light-guided LED indirect lighting device includes a receiving channel, a light-guide plate made of a high-transmittance material and fitted in the receiving channel, and a circuit board arranged between the light-guide plate and the receiving channel. The light-guide plate includes two elongated light-transmitting sections located at two lateral sides thereof and protruded beyond the receiving channel, a V-shaped reflective layer integrally formed in a front side of the light-guide plate; and an elongated groove formed on a rear side of the light-guide plate. The circuit board includes a plurality of LEDs extending into the groove to forward face the V-shaped reflective layer, such that light emitted from the LEDs is blocked and reflected by the V-shaped reflective layer to project through the two light-transmitting sections, forming indirect lighting with uniform brightness while eliminating multiple shadows and twinkling.

Abstract: A LED lighting fixture includes a cavity receiving a light guide board, and a plurality of LEDs mounted within two reinforcing parallel grooves formed in the light guide board along the length of corresponding opposite lateral sides. The light guide board further includes a clear base portion made of a light transmissive material, and a continuous reflective layer disposed over a surface of the clear base portion, the reflective layer having a portion protruding into the clear base portion. Light from the LEDs is injected transversely into the inside of the light guide board for reflection by the reflective layer to be ejected from the lighting fixture through a surface of the light guide board.

Abstract: A refreshing method suitable for a memory device is provided which includes the following steps. A sleep mode is set and the memory device cannot be read and programmed in the sleep mode. A first and a second memory cell arrays are sequentially auto-refreshed, and the steps for auto-refreshing each of the first and the second memory cell arrays individually include: during an equalization period, switching the potential of a sense line pair, a first bit line pair and a second bit line pair to a reference voltage wherein the sense line pair is not coupled to the second bit line pair, and during a refreshing period, adjusting the potential of the first and the second bit line pairs according to a refresh sequence of the first and the second memory cell arrays, thereby coupling the sense line pair to one of the first and the second bit line pairs.

Abstract: A memory controller and a decoder are provided. The decoder is adapted to the memory controller. The decoder includes a first transistor to a fourth transistor. Gates of the first to the fourth transistor are coupled to a first to a fourth control signal respectively. A first terminal and a second terminal of the first transistor are coupled to a first voltage and a first terminal of the second transistor respectively. First terminals and second terminals of the third transistor and the fourth transistor are coupled to a second terminal of the second transistor and a second voltage respectively. When the first transistor and the second transistor are turned off, a voltage of the second control signal is lower than a voltage of the first control signal. Thereby, a gate-induced drain leakage (GIDL) current of the transistors is reduced.

Abstract: A lighting lamp includes a light guide board, which is directly mounted in the cavity of a lamp holder, furniture, utensil, or the construction of a building, having a clear transmissive layer at the front side and a continuous piece of reflective layer a clear transmission layer at the front side and a reflective layer at the back side that has the shape of an umbrella surface and sloping from the periphery toward its center, and a plurality of LEDs mounted within the cavity outside the light guide board and controlled to emit light laterally into the inside of the light guide boards to provide a uniform lighting effect having an enhanced brightness without multi-image and to simulate the lighting effect of a ball lamp.

Abstract: A lighting lamp includes a light guide board, which is directly mounted in the cavity of a lamp holder, furniture, utensil, or the construction of a building, having a clear transmissive layer at the front side and a continuous piece of reflective layer a clear transmission layer at the front side and a reflective layer at the back side that has the shape of an umbrella surface and sloping from the periphery toward its center, and a plurality of LEDs mounted within the cavity outside the light guide board and controlled to emit light laterally into the inside of the light guide boards to provide a uniform lighting effect having an enhanced brightness without multi-image and to simulate the lighting effect of a ball lamp.

Abstract: A refreshing method suitable for a memory device is provided which includes the following steps. A sleep mode is set and the memory device cannot be read and programmed in the sleep mode. A first and a second memory cell arrays are sequentially auto-refreshed, and the steps for auto-refreshing each of the first and the second memory cell arrays individually include: during an equalization period, switching the potential of a sense line pair, a first bit line pair and a second bit line pair to a reference voltage wherein the sense line pair is not coupled to the second bit line pair, and during a refreshing period, adjusting the potential of the first and the second bit line pairs according to a refresh sequence of the first and the second memory cell arrays, thereby coupling the sense line pair to one of the first and the second bit line pairs.

Abstract: A memory controller and a decoder are provided. The decoder is adapted to the memory controller. The decoder includes a first transistor to a fourth transistor. Gates of the first to the fourth transistor are coupled to a first to a fourth control signal respectively. A first terminal and a second terminal of the first transistor are coupled to a first voltage and a first terminal of the second transistor respectively. First terminals and second terminals of the third transistor and the fourth transistor are coupled to a second terminal of the second transistor and a second voltage respectively. When the first transistor and the second transistor are turned off, a voltage of the second control signal is lower than a voltage of the first control signal. Thereby, a gate-induced drain leakage (GIDL) current of the transistors is reduced.

Abstract: A LED lighting fixture includes a light guide board, which is made of a high transmissive material and directly mounted in the cavity of a lamp holder, furniture, utensil, or the construction of a building, having a clear base layer at the front side and a continuous piece of reflective layer with a corrugated cross section at the back side, and a plurality of LEDs mounted within the cavity outside the light guide board and controlled to emit light transversely into the inside of the light guide boards for reflection by the reflective layer to increase the angle of illumination and to provide a uniform lighting effect having an enhanced brightness without multi-image and flashing.

Abstract: The invention provides a microfluidic apparatus for performing 2-D biomolecular separations. The microfluidic 2-D device may include first and second planar substrates which include at least a first dimension microchannel extending in a first direction and an array of second dimension microchannels extending in a second direction, preferably, orthogonal to the first dimension. The ends of at least some of the microchannels are in fluid communication with a plurality of reservoirs. The substrates may further include a number of microchannels and reservoirs. The reservoirs are in electrical communication with a plurality of electrodes and voltage power sources. The device enables two dimensional separations of proteins, DNA and other biomolecules. According to another aspect of the invention, an array of tertiary microchannels extending in a third direction may be utilized.

Abstract: A hair dyeing device includes a handle unit having a connecting section; a hair dye container removably positioned in the handle unit and having a front mouth and a rear zip lock opening; a comb unit including a base and a comb element defining a hollow space each; and an elastic absorbent member positioned in the hollow spaces of the comb unit. One end of the base of the comb unit has a sleeve for detachably fitting in the connecting section of the handle unit to engage with the mouth of the container, and a fastening element is provided on the sleeve for wrapping around the connecting section of the handle unit. The comb element has a rear portion formed into a fixing section for detachably inserting into the base and a front portion formed into upper and lower rows of teeth communicating with the second hollow space.

Abstract: A light-guide board includes a light guide plate made out of an optically transmissive material and having a transparent layer and a back reflecting layer formed integral with the back side of the transparent layer, and a plurality of reflecting baffles respectively extending from the back reflecting layer and embedded in the transparent layer for reflecting light to enhance the intensity of light and the uniformity in light intensity.

Abstract: A memory row decoder is disclosed, comprising a first depletion NMOS transistor having a second source/drain coupled to a first partially decoded signal, and a gate coupled to a second partially decoded signal, a first enhancement PMOS transistor having a second source/drain coupled to the second partially decoded signal, and a gate coupled to a first source/drain of the first depletion NMOS transistor, a first enhancement NMOS transistor having a first source/drain coupled to a first source/drain of the first enhancement PMOS transistor, a second source/drain coupled to a first reference potential, and a gate coupled to the first partially decoded signal, and a second enhancement NMOS transistor having a first source/drain coupled to the first source/drain of the first enhancement PMOS transistor, a second source/drain coupled to the first reference potential, and a gate coupled to a reset signal.

Abstract: A light-guide board includes a light guide plate made out of an optically transmissive material and having a transparent layer and a back reflecting layer formed integral with the back side of the transparent layer, and a plurality of reflecting baffles respectively extending from the back reflecting layer and embedded in the transparent layer for reflecting light to enhance the intensity of light and the uniformity in light intensity.

Abstract: A memory row decoder is disclosed, comprising a first depletion NMOS transistor having a second source/drain coupled to a first partially decoded signal, and a gate coupled to a second partially decoded signal, a first enhancement PMOS transistor having a second source/drain coupled to the second partially decoded signal, and a gate coupled to a first source/drain of the first depletion NMOS transistor, a first enhancement NMOS transistor having a first source/drain coupled to a first source/drain of the first enhancement PMOS transistor, a second source/drain coupled to a first reference potential, and a gate coupled to the first partially decoded signal, and a second enhancement NMOS transistor having a first source/drain coupled to the first source/drain of the first enhancement PMOS transistor, a second source/drain coupled to the first reference potential, and a gate coupled to a reset signal.

Abstract: A device and a method for breaking the leakage current path, wherein the leakage current is caused by a defect in a memory cell of a memory array, are provided. The device includes a column selection line, a row selection line, a switch device coupled to the column selection line, the row selection line, a power supply terminal and a memory cell. When a column turn-off signal is coupled to the column selection line and a row turn-off signal is coupled to the row selection line, the switch device is turned off and thus a power from the power supply terminal can not be coupled to the memory cell. When at least one of the column selection line and the row selection line does not receive the turn-off signal, the switch device is not turned off and the power can be coupled to the memory cell.

Abstract: Semiconductor memory devices. A semiconductor memory device includes a booster circuit generating a predetermined power voltage exceeding an external power voltage, a global power line supplying the predetermined power voltage, and a plurality of memory blocks. Each memory block has a local power line, a plurality of functional circuits coupled to the local power lines and a voltage control device coupled between the global power line and the local power line. The voltage control device outputs the predetermined power voltage or a first voltage to the functional circuits through the local power line in a first period and a second period respectively, according to a select signal, wherein the first voltage exceeds the external power voltage but is lower than the predetermined power voltage.

Abstract: A row decoder with low gate induce drain leakage current (GIDL) comprising a CMOS circuit is provided. The CMOS circuit comprises a first NMOS transistor and a first PMOS transistor. The row decoder of the present invention further comprises a second PMOS transistor and a local voltage generator. Wherein, a first source/drain of the second PMOS transistor is electrically coupled to a base of the first PMOS transistor, and a second source/drain of the second PMOS transistor is electrically coupled to a base thereof and a DC bias. Moreover, the local voltage generator provides a voltage signal to a gate of the second PMOS transistor, which controls the second PMOS transistor to work in conductive, partial conductive or open circuit mode.

Abstract: An equalizer and a method thereof and a memory device are provided. The equalizer is used for the memory device having sense amplifier, first bit line and second bit line. The equalizer includes a first switch and a second switch. The first switch is coupled between a reference voltage and the first bit line for decision whether or not transmitting the reference voltage to the first bit line according to a first control signal. The second switch is coupled between the reference voltage and the second bit line for decision whether or not transmitting the reference voltage to the second bit line according to a second control signal. Wherein, the first control signal and the second control signal are difference.