Abstract: A semiconductor structure includes a substrate and a word line. The substrate includes active regions and non-active regions that are alternately disposed in the first direction and extend in the second direction. The word line across the active regions and the non-active regions. The word line includes first conductive portions corresponding to the active regions, isolation pillars corresponding to the non-active regions, an inter-gate dielectric layer disposed on the first conductive portions and the isolation pillars, and a second conductive portion disposed on the inter-gate dielectric layer and extends in the first direction. The first conductive portions and the isolation pillars are disposed alternately in the first direction. Protruding parts of the second conductive portion correspond to the non-active regions, and the isolation pillars are on opposite sides of the corresponding protruding parts in a cross-section of the non-active region along the second direction.

Abstract: A processing apparatus for overlay shift includes a storage unit and a control unit, and is applicable to a semiconductor wafer with several inspection regions. Each of the inspection regions has several sets of overlay marks for inspection. One set of overlay marks includes an original alignment mark without any overlay shift, and several split alignment marks with predetermined overlay shifts arranged near the original alignment mark. The original after-etch inspection (AEI) overlay data of the inspection regions is stored in the storage unit. The after-develop inspection (ADI) overlay data of the original alignment mark and the split alignment marks are compared with the original AEI overlay data by the control unit, thereby acquiring ADI pre-bias data of the original alignment mark and the split alignment marks. The control unit determines whether an overlay shift compensation is performed according to the acquired ADI pre-bias data.

Abstract: A pick-up structure of a memory device and a method of manufacturing the memory device are provided. The pick-up structure includes pick-up electrode stripes. Each pickup electrode stripe includes a main body portion in the peripheral pick-up region and an extending portion extending from the main body portion to the memory cell region. The extending portion is narrower than the main body portion. The sidewall surface of the extending portion is aligned with the sidewall surface of the main body portion.

Abstract: A processing apparatus for overlay shift includes a storage unit and a control unit, and is applicable to a semiconductor wafer with several inspection regions. Each of the inspection regions has several sets of overlay marks for inspection. One set of overlay marks includes an original alignment mark without any overlay shift, and several split alignment marks with predetermined overlay shifts arranged near the original alignment mark. The original after-etch inspection (AEI) overlay data of the inspection regions is stored in the storage unit. The after-develop inspection (ADI) overlay data of the original alignment mark and the split alignment marks are compared with the original AEI overlay data by the control unit, thereby acquiring ADI pre-bias data of the original alignment mark and the split alignment marks. The control unit determines whether an overlay shift compensation is performed according to the acquired ADI pre-bias data.

Abstract: Double-exposure mask structure and photolithography method for performing a photolithography process on a substrate are provided. The substrate has a central region and a margin region. A double-exposure mask structure includes a plurality of parallel and spaced first masks corresponding to the central region, a plurality of parallel and spaced second masks corresponding to the central region, and a plurality of auxiliary masks. The second masks intersect with the first masks to form a plurality of overlapping regions. The auxiliary masks are not in contact with one another, and correspond to the Second masks to assist the overlapping regions neighboring to the auxiliary masks to have sufficient depth of focus for photolithography. With the auxiliary masks, the overlapping regions in the central region and neighboring to the margin region can have preferred photolithography and etching effect.

Abstract: Double-exposure mask structure and photolithography. method for performing a photolithography process on a substrate are provided. The substrate has a central region and a margin region. A double-exposure mask structure includes a plurality of parallel and spaced first masks corresponding to the central region, a plurality of parallel and spaced second masks corresponding to the central region, and a plurality of auxiliary masks. The second masks intersect the first masks to form a plurality of overlapping regions. The auxiliary masks are not in contact with one another, and correspond to the Second masks to assist the overlapping regions neighboring to the auxiliary masks to have sufficient depth of focus for photolithography. With the auxiliary masks, the overlapping regions in the central region and neighboring to the margin region can have preferred photolithography and etching effect.