Abstract: A method for performing adaptive multi-link aggregation dispatching control in multi-link operation architecture and associated apparatus are provided.

Abstract: Disclosed herein is a composition for removing post-etch residues in the presence of a layer comprising silicon and a dielectric layer including a silicon oxide, the composition including: (a) 0.005 to 0.3 % by weight HF; (b) 0.01 to 1 % by weight of an ammonium fluoride of formula NRE4F, where RE is H or a C1 to C4 alkyl group; (c) 5 to 30 % by weight of an organic solvent selected from the group consisting of a sulfoxide and a sulfone; (d) 70 % by weight or more water, and (e) optionally 0.01 to 1 % by weight of an ammonium compound selected from the group consisting of ammonia and a C4 to C20 quaternized aliphatic ammonium.

Abstract: A process for fabricating a capacitor is described. A template layer including a stack of at least one first layer and at least one second layer is formed over a substrate, wherein the at least one first layer and the at least one second layer have different etching selectivities and are arranged alternately. An opening is formed through the template layer. A wet etching process is performed to recess the at least one first layer relative to the at least one second layer, at the sidewall of the opening. A bottom electrode of the capacitor is formed at the bottom of the opening and on the sidewall of the opening, and then the template layer is removed.

Abstract: A method of creating a trench having a portion of a bulb-shaped cross-section in silicon is disclosed. The method comprises forming at least one trench in silicon and forming a liner in the at least one trench. The liner is removed from a bottom surface of the at least one trench to expose the underlying silicon. A portion of the underlying exposed silicon is removed to form a cavity in the silicon. At least one removal cycle is conducted to remove exposed silicon in the cavity to form a bulb-shaped cross-sectional profile, with each removal cycle comprising subjecting the silicon in the cavity to ozonated water to oxidize the silicon and subjecting the oxidized silicon to a hydrogen fluoride solution to remove the oxidized silicon. A semiconductor device structure comprising the at least one trench comprising a cavity with a bulb-shaped cross-sectional profile is also disclosed.

Abstract: A method of creating a trench having a portion of a bulb-shaped cross-section in silicon is disclosed. The method comprises forming at least one trench in silicon and forming a liner in the at least one trench. The liner is removed from a bottom surface of the at least one trench to expose the underlying silicon. A portion of the underlying exposed silicon is removed to form a cavity in the silicon. At least one removal cycle is conducted to remove exposed silicon in the cavity to form a bulb-shaped cross-sectional profile, with each removal cycle comprising subjecting the silicon in the cavity to ozonated water to oxidize the silicon and subjecting the oxidized silicon to a hydrogen fluoride solution to remove the oxidized silicon. A semiconductor device structure comprising the at least one trench comprising a cavity with a bulb-shaped cross-sectional profile is also disclosed.

Abstract: The present disclosure relates to a method of modifying a polysilicon layer, which includes the following steps. A polysilicon layer is provided. Nitrogen is incorporated into the polysilicon layer toward a predetermined depth. The polysilicon layer incorporated with nitrogen is etched, wherein after the nitrogenized polysilicon is removed, the formation of the remaining polysilicon layer is nearly indistinguishable from the formation of the polysilicon layer.

Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.

Abstract: A novel cardiovascular stent for preventing vascular stenosis is disclosed. The basic components of the cardiovascular stent of the present invention include V-shape rib unit, multi-link unit and connective ring unit. In addition, each ring rib part is formed by a plurality of double V-shape rib units that are connected together via the bridging portions of the multi-link units. Also, each connective part comprises a plurality of connective ring units. The integrally formed stent of the present invention is formed with the ring rib parts that are connected together by the connective parts.

Abstract: A process for fabricating a capacitor is described. A template layer including a stack of at least one first layer and at least one second layer is formed over a substrate, wherein the at least one first layer and the at least one second layer have different etching selectivities and are arranged alternately. An opening is formed through the template layer. A wet etching process is performed to recess the at least one first layer relative to the at least one second layer, at the sidewall of the opening. A bottom electrode of the capacitor is formed at the bottom of the opening and on the sidewall of the opening, and then the template layer is removed.

Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.

Abstract: A method of creating a trench having a portion of a bulb-shaped cross-section in silicon is disclosed. The method comprises forming at least one trench in silicon and forming a liner in the at least one trench. The liner is removed from a bottom surface of the at least one trench to expose the underlying silicon. A portion of the underlying exposed silicon is removed to form a cavity in the silicon. At least one removal cycle is conducted to remove exposed silicon in the cavity to form a bulb-shaped cross-sectional profile, with each removal cycle comprising subjecting the silicon in the cavity to ozonated water to oxidize the silicon and subjecting the oxidized silicon to a hydrogen fluoride solution to remove the oxidized silicon. A semiconductor device structure comprising the at least one trench comprising a cavity with a bulb-shaped cross-sectional profile is also disclosed.

Abstract: A novel cardiovascular stent for preventing vascular stenosis is disclosed. The basic components of the cardiovascular stent of the present invention include V-shape rib unit, multi-link unit and connective ring unit. In addition, each ring rib part is formed by a plurality of double V-shape rib units that are connected together via the bridging portions of the multi-link units. Also, each connective part comprises a plurality of connective ring units. The integrally formed stent of the present invention is formed with the ring rib parts that are connected together by the connective parts.

Abstract: A method for seamless gap filling is provided, including providing a semiconductor structure with a device layer having a gap therein, wherein the gap has an aspect ratio greater than 4. A liner layer is formed over the device layer exposed by the gap. A first un-doped oxide layer is formed over the liner layer in the gap. A doped oxide layer is formed over the first undoped oxide layer in the gap. A second un-doped oxide layer is formed over the doped oxide layer in the gap to fill the gap. An annealing process is performed on the second un-doped oxide layer, the doped oxide layer, and the first un-doped oxide to form a seamless oxide layer in the gap, wherein the seamless oxide layer has an interior doped region.

Abstract: A container device includes a skeleton having four vertical posts and four lower and four upper beams to be secured between end portions of the posts. Each of the posts includes a slot formed in one side and a groove in the other side of each of the end portions. A number of corner couplers each includes three extensions perpendicular to each other, for engaging into open ends of the beams and the posts. A number of insert panels are engaged into the end portions of the posts via the grooves of the posts and each includes a screw hole. A number of fasteners are engaged into the corner couplers, and threaded with the screw holes of the insert panels to secure the corner couplers and the beams and the posts together, and to form a parallelepiped container.

Abstract: In a method for forming STI in a silicon substrate having a pad oxide over the substrate, a hard mask is formed over the pad oxide, the hard mask and the pad oxide are patterned to form an opening, the silicon substrate is etched through the opening to form a trench, a liner oxide is formed over the trench, an STI insulator is formed in the trench, and the hard mask and the pad oxide are removed. Before the formation of the liner oxide, a clean process is performed that comprises applying silicon-consuming solution to round the top corners of the trench.

Abstract: A method of manufacturing a semiconductor device for reducing resistance of a CoSi2 layer is disclosed. First, a cobalt layer is formed on the silicon substrate, and two of the annealing treatments are conducted. The first annealing treatment is used for converting cobalt into a cobalt silicide (CoSi) layer. Next, a cap layer, about 1000 Å to 3000 Å thick, is formed on the CoSi layer, for the purpose of inhibiting re-growth of CoSi grains in the subsequent thermal processes. Then, the CoSi layer is converted into a CoSi2 layer by the second annealing treatment.

Abstract: A method of manufacturing a semiconductor device that includes providing a wafer substrate, providing an insulator over the wafer substrate; depositing a first layer over the insulator, forming a layer of dielectric material over the first silicon layer, depositing a second silicon layer over the layer of dielectric material, providing a photoresist layer over the second silicon layer, patterning and defining the photoresist layer, etching the second silicon layer, the layer of dielectric material, the first silicon layer and the insulator unmasked by the photoresist, removing the photoresist layer, and cleaning at least the etched first silicon layer with a mixture of deionized water and ozone gas.

Abstract: This invention relates to a method for making the gate dielectric layer, more particularly, to the method for making the interface between the gate dielectric layer and silicon substrate by using oxygen radicals and hydroxyl radicals. In the method, we send the wafers, which has passed through the cleaning process for the silicon substrate, to the chamber at first and then transmit the first reaction gas, which comprises the nitric monoxide and the oxygen or comprises the nitric monoxide and nitrogen, to the chamber to form a silicon nitride layer or a silicon oxynitride layer on the first surface of the silicon substrate to be a gate. Next, we transmit the second reaction gas, which comprises the oxygen and the hydrogen, to the chamber and make the second reaction gas to be dissociated into the oxygen radicals and the hydroxyl radicals.

Abstract: A method of shallow trench isolation fill-in to create the void-free trenches is disclosed. First, a liner oxide layer is formed in the trenches. Next, the silicon substrate is pre-wetted with DI water, and the liner oxide layer is etched by a chemical solution. The chemical solution is an oxide etchant, such as HF solution or BOE (buffered oxide etchant). The etching rate close to an opening of a trench is faster than a bottom of the trench. Finally, the trenches are filled with a HDP oxide layer.

Abstract: Multiple oxide layers with different thicknesses are formed on a semiconductor substrate with a silicon surface, having a first and second region. A sacrificial oxide layer is formed on the silicon surface to cover both the first region and the second region, with a mask layer formed on the surface of the sacrificial oxide layer. By defining and patterning the mask layer, a first opening and a second opening, having predetermined surface areas, are formed in portions of the first and second regions of the mask layer to expose portions of the. The sacrificial oxide layer has a surface area equal to the first predetermined surface area, and portions of the sacrificial oxide layer having a surface area equal to the second predetermined surface area. A linear nitrogen doping process is then performed to simultaneously implant nitrogen ions with a first and second predetermined concentration into the first and second region, through the first opening and the second opening, respectively.