Patents by Inventor Cheng Siew Tay

Cheng Siew Tay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8533657
    Abstract: A printed circuit board includes a group of pads suitable to be soldered to a respective group of solder-balls of a device. Each pad of the group has a crack initiation point on its perimeter at a location where cracks in a solder-ball are anticipated to start after that solder-ball is soldered to that pad. For a pad of that group having a microvia located therein, a center of that microvia is located farther than a center of that pad from its crack initiation point. For a pad of that group having a trace merging along a portion of its perimeter, that portion does not include a vicinity of that crack initiation point.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: September 10, 2013
    Assignee: Intel Corporation
    Inventors: Cheng Siew Tay, Wendy Chet Ming Ngoh, Choi Keng Chan
  • Publication number: 20110310547
    Abstract: A printed circuit board includes a group of pads suitable to be soldered to a respective group of solder-balls of a device. Each pad of the group has a crack initiation point on its perimeter at a location where cracks in a solder-ball are anticipated to start after that solder-ball is soldered to that pad. For a pad of that group having a microvia located therein, a center of that microvia is located farther than a center of that pad from its crack initiation point. For a pad of that group having a trace merging along a portion of its perimeter, that portion does not include a vicinity of that crack initiation point.
    Type: Application
    Filed: August 1, 2011
    Publication date: December 22, 2011
    Inventors: Cheng Siew TAY, Wendy Chet Ming NGOH, Choi Keng CHAN
  • Patent number: 8079011
    Abstract: A printed circuit board includes a group of pads suitable to be soldered to a respective group of solder-balls of a device. Each pad of the group has a crack initiation point on its perimeter at a location where cracks in a solder-ball are anticipated to start after that solder-ball is soldered to that pad. For a pad of that group having a microvia located therein, a center of that microvia is located farther than a center of that pad from its crack initiation point. For a pad of that group having a trace merging along a portion of its perimeter, that portion does not include a vicinity of that crack initiation point.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: December 13, 2011
    Assignee: Intel Corporation
    Inventors: Cheng Siew Tay, Wendy Chet Ming Ngoh, Choi Keng Chan
  • Patent number: 7789285
    Abstract: In one embodiment, a method is provided. The method comprises filling a microvia formed in a bond pad with solder paste comprising solder balls of the first size; and coating the bond pad with solder paste comprising solder balls of the second size, wherein the second size is greater than the first size.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: September 7, 2010
    Assignee: Intel Corporation
    Inventors: Cheng Siew Tay, Pek Chew Tan, Swee Kian Cheng, Eng Hooi Yap
  • Patent number: 7642660
    Abstract: A method and apparatus is provided that pertains to resisting crack initiation and propagation in electrical interconnections between components and substrates in ball grid array microelectronic packages. A hybrid of dielectric defined and non-dielectric defined electrical interconnects reduces the potential for electrical interconnection failure without having to control the dielectric defined interconnect ratio of substrates. In addition selective orientation of the dielectric defined edge portion of the electrical interconnect away from the point where cracks initiate resists crack propagation and component failure.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: January 5, 2010
    Inventors: Cheng Siew Tay, Swee Kian Cheng, Eng Huat Goh
  • Patent number: 7400040
    Abstract: An apparatus and system, as well as fabrication methods therefor, may include a substrate coupled to a first material and a second material. The first and second materials may comprise adjacent metals, and may have different coefficients of thermal expansion sufficient to reduce the amount of substrate warp that can occur due to heating and cooling.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: July 15, 2008
    Assignee: Intel Corporation
    Inventors: Eng Hooi Yap, Cheng Siew Tay, Pek Chew Tan
  • Patent number: 7331503
    Abstract: In one embodiment, a method is provided. The method comprises filling a microvia formed in a bond pad with solder paste comprising solder balls of the first size; and coating the bond pad with solder paste comprising solder balls of the second size, wherein the second size is greater than the first size.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: February 19, 2008
    Assignee: Intel Corporation
    Inventors: Cheng Siew Tay, Pek Chew Tan, Swee Kian Cheng, Eng Hooi Yap
  • Patent number: 7326859
    Abstract: A printed circuit board includes a group of pads suitable to be soldered to a respective group of solder-balls of a device. Each pad of the group has a crack initiation point on its perimeter at a location where cracks in a solder-ball are anticipated to start after that solder-ball is soldered to that pad. For a pad of that group having a microvia located therein, a center of that microvia is located farther than a center of that pad from its crack initiation point. For a pad of that group having a trace merging along a portion of its perimeter, that portion does not include a vicinity of that crack initiation point.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: February 5, 2008
    Assignee: Intel Corporation
    Inventors: Cheng Siew Tay, Wendy Chet Ming Ngoh, Choi Keng Chan
  • Patent number: 7242084
    Abstract: Apparatuses and associated methods to improve integrated circuit packaging are generally described. More specifically, apparatuses and associated methods to improve solder joint reliability are described. In this regard, according to one example embodiment, one or more strengthening pin(s) are coupled to the periphery of a package substrate, the strengthening pin(s) capable of coupling to a circuit board.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: July 10, 2007
    Assignee: Intel Corporation
    Inventors: Chee Wai Wong, Cheng Siew Tay
  • Patent number: 7173342
    Abstract: A method and apparatus is provided that pertains to resisting crack initiation and propagation in electrical interconnections between components and substrates in ball grid array microelectronic packages. A hybrid of dielectric defined and non-dielectric defined electrical interconnects reduces the potential for electrical interconnection failure without having to control the dielectric defined interconnect ratio of substrates. In addition selective orientation of the dielectric defined edge portion of the electrical interconnect away from the point where cracks initiate resists crack propagation and component failure.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: February 6, 2007
    Assignee: Intel Corporation
    Inventors: Cheng Siew Tay, Swee Kian Cheng, Eng Huat Goh
  • Publication number: 20040256720
    Abstract: An apparatus and system, as well as fabrication methods therefor, may include a substrate coupled to a first material and a second material. The first and second materials may comprise adjacent metals, and may have different coefficients of thermal expansion sufficient to reduce the amount of substrate warp that can occur due to heating and cooling.
    Type: Application
    Filed: June 10, 2003
    Publication date: December 23, 2004
    Applicant: Intel Corporation
    Inventors: Eng Hooi Yap, Cheng Siew Tay, Pek Chew Tan
  • Publication number: 20040113285
    Abstract: A method and apparatus is provided that pertains to resisting crack initiation and propagation in electrical interconnections between components and substrates in ball grid array microelectronic packages. A hybrid of dielectric defined and non-dielectric defined electrical interconnects reduces the potential for electrical interconnection failure without having to control the dielectric defined interconnect ratio of substrates. In addition selective orientation of the dielectric defined edge portion of the electrical interconnect away from the point where cracks initiate resists crack propagation and component failure.
    Type: Application
    Filed: December 17, 2002
    Publication date: June 17, 2004
    Inventors: Cheng Siew Tay, Swee Kian Cheng, Eng Huat Goh