Abstract: A method of operating a memory circuit includes generating, by a first memory cell array, a first current in response to a first voltage, generating, by a tracking circuit, a second set of leakage currents, generating, by a first current source, a second write current, and mirroring, by a first current mirror. The first current includes a first set of leakage currents and a first write current. The first current is in a first path with a second current in a second path. The second current includes the second set of leakage currents and the second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents. The second set of leakage currents is configured to track the first set of leakage currents of the first memory cell array.

Abstract: A slide rail assembly includes a first rail, a second rail, an aid-sliding device, a compensating device and a third rail. The aid-sliding device is movably mounted between the first rail and the second rail. The compensating device is movably mounted on the second rail. The second rail is configured to be movably mounted on the third rail. The compensating device is configured to compensating an error of a relative position of the first rail and the second rail.

Abstract: An image sensor structure and methods of forming the same are provided. An image sensor structure according to the present disclosure includes a semiconductor substrate including a photodiode, a transfer gate transistor disposed over the semiconductor substrate and having a first channel area, a first dielectric layer disposed over the semiconductor substrate, a semiconductor layer disposed over the first dielectric layer, a source follower transistor disposed over the semiconductor layer and having a second channel area, a row select transistor disposed over the semiconductor layer and having a third channel area, and a reset transistor disposed over the semiconductor layer and having a fourth channel area. The second channel area is greater than the first channel area, the third channel area or the fourth channel area.

Abstract: A temperature-corrected biochemical sensor includes an optical resonator disposed proximate a single-mode optical fiber, the optical resonator being optically coupled to the optical fiber to receive optical whispering-gallery output light; a sensor detection system arranged to receive and detect the optical whispering-gallery output light to provide sensor signals; a temperature-correcting optical system to provide a reference beam of light to be combined at least partially coherently with a return light from the resonator to provide an interference light and convert, the interference light to temperature-correction signals; a data storage device comprising temperature calibration data for at least the optical fiber and the optical resonator; and a data processing system to calculate at least one physical property of a particle in contact with the optical resonator using the sensor signals such that the calculated physical property is temperature corrected using the temperature calibration data and the temper

Abstract: A wideband antenna system includes a first metal radiation portion, having a coupling distance with a second metal radiation portion; a first feeding contact and a second feeding contact, electrically connected to the first metal radiation portion and the second metal radiation portion respectively, and close to the coupling distance; a first ground contact, electrically connected to the second metal radiation portion; a second ground contact, electrically connected to the first metal radiation portion; an impedance tuner, electrically connected to the first feeding contact, the second feeding contact, the first ground contact, the second ground contact, and a radio frequency signal source, to switch the first metal radiation portion and the second metal radiation portion; an aperture contact, electrically connected to the first metal radiation portion; and an aperture tuner, electrically connected to the aperture contact.

Abstract: A production line operation forecast method and a production line operation forecast system are provided. The production line operation forecast method includes the following steps: obtaining an online production line work-in-process map at a time point, generating candidate simulated dispatch decisions based on the online production line work-in-process map, and inferring production-line work-in-process map changes of the candidate simulated dispatch decisions at a next time point; inputting the production-line work-in-process map changes to a forecast model, such that the forecast model outputs simulated production line operation health indicators of the candidate simulated dispatch decisions at the next time point; and selecting one of the candidate simulated dispatch decisions as a scheduling dispatch decision.

Abstract: Provided is a recognition method of 3D vein pattern including the following steps. A plurality of first light beams are emitted by a recognition device to a wrist of a user. A plurality of first reflected light beams from the wrist are received by the recognition device to form a first 3D vein pattern of the wrist. Differences between the first 3D vein pattern and a wrist vein pattern of a database are compared to identify an identity or a gesture of the user. A recognition device of 3D vein pattern is also provided.

Abstract: A voltage regulator circuit is provided. The voltage regulator circuit includes a voltage regulator configured to provide an output voltage at an output terminal. A plurality of macros are connectable at a plurality of connection nodes of a connector connected to the output terminal of the voltage regulator. A feedback circuit having a plurality of feedback loops is connectable to the plurality of connection nodes. The feedback loop of the plurality of feedback loops, when connected to a connection node of the plurality of connection nodes, is configured to provide an instantaneous voltage of the connection node as a feedback to the voltage regulator. The voltage regulator is configured, in response to the instantaneous voltage, regulate the output voltage to maintain the instantaneous voltage of the connection node approximately equal to a reference voltage.

Abstract: The present disclosure describes a semiconductor device having a dielectric structure between a source/drain (S/D) structure and a contact structure. The semiconductor device includes a S/D structure on a substrate, a dielectric structure on a top surface of the S/D structure, and a S/D contact structure on the S/D structure and the dielectric structure. A portion of the S/D contact structure is in contact with a top surface of the dielectric structure.

Abstract: An electrostatic discharge protection device includes a substrate, a well region of a first conductivity type in the substrate, a drain field region and a source field region of a second conductivity type in the well region, a gate structure on the well region and between the drain field region and the source field region, a drain contact region and a source contact region of the second conductivity type respectively in the drain field region and the source field region, a first isolation region in the drain field region and between the drain contact region and the gate structure, and a drain doped region of the first conductivity in the drain field region and between a portion of a bottom surface of the drain contact region and the drain field region.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple first semiconductor nanostructures over a substrate and multiple second semiconductor nanostructures over the substrate. The semiconductor device structure also includes a dielectric structure between the first semiconductor nanostructures and the second semiconductor nanostructures. The semiconductor device structure further includes a metal gate stack wrapped around the first semiconductor nanostructures and the second semiconductor nanostructures. The metal gate stack has a gate dielectric layer and a gate electrode. The gate dielectric layer extends along a sidewall of a lower portion of the dielectric structure. A topmost surface of the gate dielectric layer is between a topmost surface of the first semiconductor nanostructures and a topmost surface of the dielectric structure.

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

Abstract: A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill, wherein the first liner layer surrounds the conductive fill.

Abstract: A slide rail assembly includes a first rail, a second rail, an elastic member, a movable member and an electronic module. The second rail is movable relative to the first rail. When the second rail is located at a retracted position relative to the first rail and when the movable member is in a locking state, the elastic member is configured to be locked to accumulate the elastic force. The electronic module includes a driving device configured to drive the movable member to switch from the locking state to an unlocking state, in order to release the elastic force of the elastic member, such that the second rail is moved from the retracted position along an opening direction relative to the first rail in response to the elastic force of the elastic member.

Abstract: An imaging lens module includes an imaging lens, an adjustable aperture module, a first spacer and a second spacer. The adjustable aperture module is disposed between an object-side lens group and an image-side lens group of the imaging lens and comprises a blade assembly, fixed shafts, a movable component and a driving mechanism. The blade assembly includes at least two light-blocking blades forming a light pass aperture. The driving mechanism is to rotate the movable component in a circumferential direction, allowing the blade assembly to move relative to the fixed shafts for varying an aperture size of the light pass aperture. The fixed shafts are disposed on the first spacer. The second spacer and the first spacer together form an inner space in which the adjustable aperture module is accommodated. The second spacer receives and is in physical contact with the object-side lens group.

Abstract: The present disclosure provides a system for signal optimization adjustment based on different heat source information. The system includes a plurality of heat source measurers, a first system chip, a second system chip, an electrical interconnection, and a bit error risk evaluator. The first system chip includes a signal transmitter, and the second system chip includes a signal receiver. The second system chip provides an electrical characteristic state of the signal receiver, and a signal adjustment information of the signal transmitter and/or the signal receiver. The bit error risk evaluator performs a signal optimization adjustment for an electrical characteristic of the signal receiver according to the electrical characteristic state. The present disclosure further provides a method for signal optimization adjustment.

Abstract: The application provides a method and a memory device for performing wear leveling in a memory device. The method includes: receiving data to be written transmitted by a host in the memory device; predicting the data to be written as a first type of data or a second type of data; referencing an erase count table in an erase count table buffer of the memory device; and when the data to be written is predicted as the first type of data, writing the data to be written into the block with a highest erase count among these blocks, and when the data to be written is predicted as the second type of data, writing the data to be written into the block with a lowest erase count among these blocks.

Abstract: The present disclosure provides a display device and a method for manufacturing a display device. The method for manufacturing a display device of the present disclosure includes: forming a light emitting layer, a first metal layer and a protective layer on a substrate, wherein the first metal layer is located between the light emitting layer and the protective layer; forming a release layer covering over the light emitting layer, the first metal layer and the protective layer; removing a first portion of the release layer to expose the light emitting layer and the first portion of the first metal layer; and forming a first encapsulation layer covering the light emitting layer, a first portion of the first metal layer and a second portion of the release layer. A thickness of the first encapsulation layer on the light emitting layer is substantially equal to a thickness of the first encapsulation layer on the first portion of the first metal layer.

Abstract: A memory circuit includes a first driver circuit, a memory cell array including a first column of memory cells, a first transistor coupled between the first driver circuit and the memory cell array, a second driver circuit, a first column of tracking cells and a header circuit coupled to the first driver circuit and the second driver circuit. The first transistor is configured to receive a first select signal. The first column of tracking cells is configured to track a leakage current of the first column of memory cells, and is coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit.

Abstract: A temperature-sensitive cell culture composition is provided. The temperature-sensitive cell culture composition includes a hydrogel, a cellulose, a gelatin and a collagen. Based on 1 part by weight of the collagen, a content of the hydrogel is between 0.03 parts by weight and 60 parts by weight, a content of the cellulose is between 150 parts by weight and 360 parts by weight, and a content of the gelatin is between 21 parts by weight and 12 parts by weight. In addition, a method for using the temperature-sensitive cell culture composition, a method for forming the temperature-sensitive cell culture composition, and a use of the temperature-sensitive cell culture composition are also provided.