Abstract: An electronic package module including a circuit substrate, an electronic component disposed on the circuit substrate and a molding compound is provided. The molding compound encapsulates the circuit substrate and the electronic component. The circuit substrate includes a first circuit layer and a first insulation layer covering on the first circuit layer. The first insulation layer has a boundary surface where a second circuit layer is disposed. A second insulation layer covers a part of the second circuit layer while the insulation layer bares a region surrounding the perimeter of the boundary surface. The molding compound directly contacts the region and the second insulation layer.

Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.

Abstract: An LDMOS transistor device includes a stepped isolation structure over a substrate, a gate electrode disposed over a portion of the stepped isolation structure, a source region disposed in the substrate, and a drain region disposed in the substrate. The stepped isolation structure includes a first portion having a first thickness, and a second portion having a second thickness greater than the first thickness. The second portion includes dopants. The drain region is adjacent to the stepped isolation structure.

Abstract: A power metal-oxide-semiconductor structure includes a semiconductor substrate, a gate electrode disposed above the semiconductor substrate, a field plate, and an electrically conductive pattern. The gate electrode and the field plate are disposed above the semiconductor substrate, the electrically conductive pattern is disposed between the field plate and the semiconductor substrate in a vertical direction, and the field plate and the electrically conductive pattern are located at the same side of the gate electrode in a horizontal direction. A manufacturing method of a power metal-oxide-semiconductor structure includes the following steps. The electrically conductive pattern and the field plate are formed above a first region of the semiconductor substrate. Subsequently, the gate electrode is formed above the first region of the semiconductor substrate.

Abstract: A memory device includes a substrate and a plurality of word lines. The word lines are disposed on the substrate. The word lines extend in the first direction and are arranged in the second direction. The first direction intersects the second direction. The memory device further includes a first sub-select gate extending in the first direction and separated from the outermost word line in the second direction. One end of the first sub-select gate has a first width in the second direction. The major portion of the first sub-select gate has a second width in the second direction. The second width is greater than the first width.

Abstract: An imaging lens assembly module includes an imaging lens element set, a lens carrier and a light blocking structure. The imaging lens element set has an optical axis. At least one lens element of the lens elements is disposed in the lens carrier. The light blocking structure includes a light blocking opening. The optical axis passes through the light blocking opening, and the light blocking opening includes at least two arc portions and a shrinking portion. Each of the arc portions has a first curvature radius for defining a maximum diameter of the light blocking opening. The shrinking portion is connected to the arc portions for forming the light blocking opening into a non-circular shape. The shrinking portion includes at least one protruding arc which extends and shrinks gradually from the shrinking portion to the optical axis, and the protruding arc has a second curvature radius.

Abstract: A light-emitting device is provided. The light-emitting device generates a white light and includes at least one light-emitting diode. The at least one light-emitting diode generates a light beam with a broadband blue spectrum and includes a first semiconductor layer, a second semiconductor layer and a multiple quantum well structure. The multiple quantum well structure is located between the first semiconductor layer and the second semiconductor layer, and includes well layers and barrier layers. The well layers include a first well layer, a second well layer and third well layers different in indium concentrations. The first well layer has the largest indium concentration, and the third well layers have the smallest indium concentration. Three of the well layers that are closest to the first semiconductor layer are the third well layers, and the first well layer is closer to the second semiconductor layer than the first semiconductor layer.

Abstract: The invention provides a circuit board structure and a manufacturing method thereof. The circuit board structure includes a line portion, a first insulating layer, and a conductive terminal. The first insulating layer is disposed on the line portion. The conductive terminal is disposed on the first insulating layer and embedded in the first insulating layer to be electrically connected with the line portion. The conductive terminal includes a first portion, a second portion, and a third portion. The first portion protrudes from a surface of the first insulating layer. The second portion is embedded in the first insulating layer and connected to the first portion. The third portion is disposed between the line portion and the second portion. A width of the second portion is greater than a width of the third portion.

Abstract: Disclosed is a package structure including a circuit board, a co-packaged optics (CPO) substrate, an application specific integrated circuit (ASIC) assembly, a glass interposer, an electronic integrated circuit (EIC) assembly, a photonic integrated circuit (PIC) assembly, and an optical fiber assembly. The CPO substrate is configured on the circuit board, and the ASIC assembly is configured on the CPO substrate. The glass interposer is configured on the CPO substrate and includes an upper surface, a lower surface, a cavity, and at least one through glass via (TGV). The EIC assembly is configured on the upper surface of the glass interposer and electrically connected to the glass interposer. The PIC assembly is configured in the cavity of the glass interposer and electrically connected to the glass interposer. The optical fiber assembly is configured on the lower surface of the glass interposer and optically connected to the PIC assembly.

Abstract: A method for preventing a railcar from overturning, including: enabling a side of a carriage of a vehicle body to include a side wing, so that airflow generates a centripetal force due to a difference in pressure on two surfaces of an airfoil of the side wing when the vehicle body travels through a curve portion of a track, to counteract a centrifugal force on the vehicle body by the centripetal force. An anti-overturning railcar for implementing the foregoing method is also revealed.

Abstract: A manufacturing method of a micro-electromechanical system acoustic sensor includes: forming an insulating layer and two first electrodes on a base plate, the two first electrodes being spaced apart from each other; arranging a first sacrificial layer on the insulating layer and the two first electrodes, and forming at least one first recess in the first sacrificial layer respectively above the two first electrodes; arranging a second sacrificial layer on the first sacrificial layer and the at least two first recesses, forming two second recesses spaced apart in the second sacrificial layer, and making the two second recesses respectively communicate with the corresponding at least one first recess to form two recess spaces; filling the two recess spaces respectively with a material to form two second electrodes; and removing all the first sacrificial layer and the second sacrificial layer.

Abstract: Provided is a memory device, including: a substrate; a plurality of word lines, extending in a first direction, arranged in a second direction, disposed on the substrate; a dummy structure, adjacent to ends of the word lines, disposed on the substrate, wherein the dummy structure includes a main part that extends in the second direction; and a plurality of extension parts, extending in the first direction, connected to the main part, and interposed between the main part and the word lines.

Abstract: A micro-electromechanical system (MEMS) acoustic sensor includes: a silicon substrate layer; an insulation layer, arranged above the silicon substrate layer; two first electrode layers, respectively arranged above the insulation layer and arranged opposite to each other at intervals; and two second electrode layers, respectively arranged above the two first electrode layers. Each of the second electrode layers is provided with at least one support member connected to the corresponding first electrode layer, and forms an acoustic flow channel together with a part of the insulation layer and the two first electrode layers. The each second electrode layer has a front section and a rear section. The front section forms a diverging first cambered surface. The rear section forms a tapered second cambered surface.

Abstract: Provided is a memory device, including: a substrate; a plurality of word lines, extending in a first direction, arranged in a second direction, disposed on the substrate; a dummy structure, adjacent to ends of the word lines, disposed on the substrate, wherein the dummy structure includes a main part that extends in the second direction; and a plurality of extension parts, extending in the first direction, connected to the main part, and interposed between the main part and the word lines.

Abstract: A pick-up structure for a memory device and method for manufacturing memory device are provided. The pick-up structure includes a substrate and a plurality of pick-up electrode strips. The substrate has a memory cell region and a peripheral pick-up region adjacent thereto. The pick-up electrode strips are parallel to a first direction and arranged on the substrate in a second direction. The second direction is different from the first direction. Each pick-up electrode strip includes a main part in the peripheral pick-up region and an extension part extending from the main part to the memory cell region. The main part is defined by fork-shaped patterns of a first mask layer. The extension part has a width less than that of the main part, and the extension part has a side wall surface aligned with a side wall surface of the main part.

Abstract: A flash memory device is provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.

Abstract: A method for forming a semiconductor structure is provided. The method includes: forming first and second hard mask layers and a target layer on a substrate; patterning the second hard mask layer to form patterned second hard masks including a second wide mask and second narrow masks; and forming spacers on sidewalls of the second wide mask and the second narrow masks. Then, a photoresist layer is formed to cover the second wide mask and the spacers on the sidewalls of the second wide mask. The second narrow masks and the photoresist layer are removed. And, the first hard mask layer is etched with the spacers and the second wide mask together as a mask to form patterned first hard masks on the target layer, wherein the spacers define a first line width, and the second wide mask and the pair of spacers define a second line width.

Abstract: A flash memory device and its manufacturing method are provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.

Abstract: A method for forming a semiconductor structure is provided. The method includes: forming first and second hard mask layers and a target layer on a substrate; patterning the second hard mask layer to form patterned second hard masks including a second wide mask and second narrow masks; and forming spacers on sidewalls of the second wide mask and the second narrow masks. Then, a photoresist layer is formed to cover the second wide mask and the spacers on the sidewalls of the second wide mask. The second narrow masks and the photoresist layer are removed. And, the first hard mask layer is etched with the spacers and the second wide mask together as a mask to form patterned first hard masks on the target layer, wherein the spacers define a first line width, and the second wide mask and the pair of spacers define a second line width.

Abstract: A method for forming a memory device is provided. The method includes forming a floating gate on a substrate, and forming a control gate on the floating gate. The method also includes forming a mask layer on the control gate, and forming a spacer on a sidewall of the mask layer, wherein a sidewall of the control gate and a sidewall of the floating gate is covered by the spacer. The method further includes performing an ion implantation process to implant a dopant into a top portion of the spacer, and performing a wet etching process to expose the sidewall of the control gate.