Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

Abstract: A testing method including the following steps is provided. A lead frame is provided, wherein the lead frame includes a frame body and a plurality of lead frame units which are connected with each other through the frame body and are arranged in array. Each of the lead frame units includes at least one first pin connected with the frame body and a plurality of second pins which are connected with each other. A plurality of controllers are bonded with the lead frame units and each of the controllers is electrically connected with the corresponding lead frame unit. The frame body of each of the lead frame units is electrically isolated from the second pins. A first electrical testing is performed to each of the lead frame units carrying the controllers.

Abstract: A carrier array adapted for carrying a plurality of chips is provided. The carrier array includes a lead frame, controllers and first packages. The lead frame includes a frame body and a plurality of lead frame units. The lead frame units are connected with each other through the frame body and arranged in an array. Each of the lead frame units includes at least one first pin connected with the frame body and a plurality of second pins not connected with the frame body. The controllers are disposed on the lead frame units, and electrically connected with the corresponding lead frame units, respectively. Each of the first packages is disposed on the lead frame, and respectively has an opening to expose a portion region of the corresponding lead frame unit, and the openings are adapted for accommodating the chips. A light emitting diode package is also provided.

Abstract: A carrier array adapted for carrying a plurality of chips is provided. The carrier array includes a lead frame, controllers and first packages. The lead frame includes a frame body and a plurality of lead frame units. The lead frame units are connected with each other through the frame body and arranged in an array. Each of the lead frame units includes at least one first pin connected with the frame body and a plurality of second pins not connected with the frame body. The controllers are disposed on the lead frame units, and electrically connected with the corresponding lead frame units, respectively. Each of the first packages is disposed on the lead frame, and respectively has an opening to expose a portion region of the corresponding lead frame unit, and the openings are adapted for accommodating the chips. A light emitting diode package is also provided.

Abstract: A testing method including the following steps is provided. A lead frame is provided, wherein the lead frame includes a frame body and a plurality of lead frame units which are connected with each other through the frame body and are arranged in array. Each of the lead frame units includes at least one first pin connected with the frame body and a plurality of second pins which are connected with each other. A plurality of controllers are bonded with the lead frame units and each of the controllers is electrically connected with the corresponding lead frame unit. The frame body of each of the lead frame units is electrically isolated from the second pins. A first electrical testing is performed to each of the lead frame units carrying the controllers.

Abstract: A control circuit of a multi-mode buck-boost switching regulator and a method thereof are provided. The control circuit imposes ON/OFF timing sequences on switches according to the relationship between two controlling triangle waves and the load fluctuation. In each working cycle of each mode of the regulator, at most two switches perform switching operations. The control circuit is simple to design, which only includes simple digital elements, such as comparators, logic gates etc., instead of complicated analog circuits.

Abstract: A control circuit of a multi-mode buck-boost switching regulator and a method thereof are provided. The control circuit imposes ON/OFF timing sequences on switches according to the relationship between two controlling triangle waves and the load fluctuation. In each working cycle of each mode of the regulator, at most two switches perform switching operations. The control circuit is simple to design, which only includes simple digital elements, such as comparators, logic gates etc., instead of complicated analog circuits.

Abstract: A method for forming a contact or via plug is described. A dielectric layer and a patterned photoresist layer are sequentially formed on a substrate. A portion of the exposed dielectric layer is removed to form a first opening. A first liner is formed on the surfaces of the photoresist layer. An anisotropic etching process is conducted using the first liner and the photoresist layer as a mask to remove a portion of the dielectric layer under the first opening to form a second opening incorporating the first opening. A second liner is formed on the photoresist layer covering the first liner. Then, the above etching step is repeated to form a third opening that incorporates the second opening and exposes the substrate. The second liner, the first liner and the photoresist layer are removed, and then a conductive material is filled into the third opening to form a contact or via plug.

Abstract: A method for forming a contact or via plug is described. A dielectric layer and a patterned photoresist layer are sequentially formed on a substrate. A portion of the exposed dielectric layer is removed to form a first opening. A first liner is formed on the surfaces of the photoresist layer. An anisotropic etching process is conducted using the first liner and the photoresist layer as a mask to remove a portion of the dielectric layer under the first opening to form a second opening incorporating the first opening. A second liner is formed on the photoresist layer covering the first liner. Then, the above etching step is repeated to form a third opening that incorporates the second opening and exposes the substrate. The second liner, the first liner and the photoresist layer are removed, and then a conductive material is filled into the third opening to form a contact or via plug.