Patents by Inventor Cheng-Te Chou
Cheng-Te Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240094052Abstract: An optical module is disclosed. The optical module includes a carrier, an optical emitter disposed over the carrier, and a monitor disposed over the carrier and configured to adjust a property of a first light emitted from the optical emitter.Type: ApplicationFiled: September 20, 2022Publication date: March 21, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Kuo Sin HUANG, Tien-Chia LIU, Ko-Fan TSAI, Cheng-Te CHOU, Yan-Te CHOU
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Patent number: 11822085Abstract: The present disclosure provides an optical adaptive device and a wearable device. The optical adaptive device includes a carrier, a first light adjusting element, and a second light adjusting element. The first light adjusting element is in or on the carrier and configured to focus a first light from a first article on a visual area. The second light adjusting element is in or on the carrier and configured to focus a second light from a second article on the visual area. The second article is further away from the area than the first article.Type: GrantFiled: September 3, 2021Date of Patent: November 21, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ko-Fan Tsai, Tien-Chia Liu, Kuo Sin Huang, Cheng-Te Chou
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Publication number: 20230074105Abstract: The present disclosure provides an optical adaptive device and a wearable device. The optical adaptive device includes a carrier, a first light adjusting element, and a second light adjusting element. The first light adjusting element is in or on the carrier and configured to focus a first light from a first article on a visual area. The second light adjusting element is in or on the carrier and configured to focus a second light from a second article on the visual area. The second article is further away from the area than the first article.Type: ApplicationFiled: September 3, 2021Publication date: March 9, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ko-Fan TSAI, Tien-Chia LIU, Kuo Sin HUANG, Cheng-Te CHOU
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Patent number: 8922026Abstract: The invention provides A chip package, comprising: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region, and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; and a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures, wherein the heavily doped regions are disposed in a carrier substrate which is bonded to the first surface of the semiconductor substrate.Type: GrantFiled: July 19, 2012Date of Patent: December 30, 2014Inventors: Chien-Hung Liu, Cheng-Te Chou
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Patent number: 8748949Abstract: The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.Type: GrantFiled: November 5, 2010Date of Patent: June 10, 2014Inventors: Chien-Hung Liu, Cheng-Te Chou
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Patent number: 8633582Abstract: A chip package is disclosed. The package includes a carrier substrate and at least one semiconductor chip thereon. The semiconductor chip has a plurality of conductive pads, where a plurality of first redistribution layers (RDLs) is disposed thereon and is electrically connected thereto. A single-layer insulating structure covers the carrier substrate and the semiconductor chip, having a plurality of openings exposing the plurality of first RDLs. A plurality of second RDLs is disposed on the single-layer insulating structure and is electrically connected to the plurality of first RDLs. A passivation layer is disposed on the single-layer insulating structure and the plurality of second RDLs, having a plurality of openings exposing the plurality of second RDLs. A plurality of conductive bumps is correspondingly disposed in the plurality of openings to be electrically connected to the plurality of second RDLs. A fabrication method of the chip package is also disclosed.Type: GrantFiled: February 9, 2010Date of Patent: January 21, 2014Inventors: Shu-Ming Chang, Cheng-Te Chou
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Patent number: 8497534Abstract: The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.Type: GrantFiled: May 26, 2010Date of Patent: July 30, 2013Inventors: Chien-Hung Liu, Cheng-Te Chou
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Patent number: 8431950Abstract: A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed on a first surface of the light emitting device chip and a second electrode layer is disposed on a second surface of the light emitting device chip, in which the first surface and the second surface are not coplanar. A first conductive trace is electrically connected to the first electrode layer and a second conductive trace is electrically connected to the second electrode layer. At least the first conductive trace or the second conductive trace is formed along the chip side and the substrate side simultaneously.Type: GrantFiled: May 22, 2009Date of Patent: April 30, 2013Inventors: Chia-Lun Tsai, Ching-Yu Ni, Wen-Cheng Chien, Shang-Yi Wu, Cheng-Te Chou
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Publication number: 20120280389Abstract: The invention provides A chip package, comprising: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region, and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; and a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures, wherein the heavily doped regions are disposed in a carrier substrate which is bonded to the first surface of the semiconductor substrate.Type: ApplicationFiled: July 19, 2012Publication date: November 8, 2012Inventors: Chien-Hung LIU, Cheng-Te Chou
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Publication number: 20110042796Abstract: A chip package is disclosed. The package includes a carrier substrate and at least one semiconductor chip thereon. The semiconductor chip has a plurality of conductive pads, where a plurality of first redistribution layers (RDLs) is disposed thereon and is electrically connected thereto. A single-layer insulating structure covers the carrier substrate and the semiconductor chip, having a plurality of openings exposing the plurality of first RDLs. A plurality of second RDLs is disposed on the single-layer insulating structure and is electrically connected to the plurality of first RDLs. A passivation layer is disposed on the single-layer insulating structure and the plurality of second RDLs, having a plurality of openings exposing the plurality of second RDLs. A plurality of conductive bumps is correspondingly disposed in the plurality of openings to be electrically connected to the plurality of second RDLs. A fabrication method of the chip package is also disclosed.Type: ApplicationFiled: February 9, 2010Publication date: February 24, 2011Inventors: Shu-Ming CHANG, Cheng-Te Chou
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Publication number: 20110042807Abstract: The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.Type: ApplicationFiled: November 5, 2010Publication date: February 24, 2011Inventors: Chien-Hung LIU, Cheng-Te Chou
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Publication number: 20110042804Abstract: The invention provides a chip package and fabrication method thereof. In one embodiment, the chip package includes: a semiconductor substrate having opposite first and second surfaces, at least one bond pad region and at least one device region; a plurality of conductive pad structures disposed on the bond pad region at the first surface of the semiconductor substrate; a plurality of heavily doped regions isolated from one another, underlying and electrically connected to the conductive pad structures; and a plurality of conductive bumps underlying the heavily doped regions and electrically connected to the conductive pad structures through the heavily-doped regions.Type: ApplicationFiled: May 26, 2010Publication date: February 24, 2011Inventors: Chien-Hung Liu, Cheng-Te Chou
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Publication number: 20090289273Abstract: A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed on a first surface of the light emitting device chip and a second electrode layer is disposed on a second surface of the light emitting device chip, in which the first surface and the second surface are not coplanar. A first conductive trace is electrically connected to the first electrode layer and a second conductive trace is electrically connected to the second electrode layer. At least the first conductive trace or the second conductive trace is formed along the chip side and the substrate side simultaneously.Type: ApplicationFiled: May 22, 2009Publication date: November 26, 2009Inventors: Chia-Lun Tsai, Ching-Yu Ni, Wen-Cheng Chien, Shang-Yi Wu, Cheng-Te Chou