Abstract: A method for backside grinding a semiconductor wafer and forming a contamination free bonding pad connection. The method comprises forming a passivation layer over a metal layer. Applying a photoresist pattern with an opening which will define a bonding pad area and removing the passivation layer exposed in the opening. Next, the photoresist is removed, but a polymer residue is often formed on the surfaces of the passivation layer surrounding the bonding pad. In a novel step, the residue is removed using an etchant containing Dimethylsulfoxide (D.M.D.O.) aud Monoethanolamine (M.E.A.) and is followed by au oxygen plasma treatment. Next, the device side of the wafer is covered with a protective tape and the backside of the wafer is grouud back. The tape is removed revealing a contamination free bonding pad area. A bonding connection is then made to the bonding pad.

Abstract: A method is described for fabricating an integrated circuit with polycide gate electrodes in which there is no delamination of the overlying dielectric layer. A polysilicon layer over a gate dielectric is provided on a silicon substrate. A silicide layer is formed over the polysilicon layer using WF.sub.6 and SiH.sub.4 as the reaction gases. The silicide and polysilicon layers are patterned to form polycide gate electrodes. The substrate is annealed initially in an inert gas atmosphere to remove excess fluorine gas, then in an oxygen atmosphere. Lightly doped source and drain ion implants are performed. Spacers are formed on the sidewalls of the polycide gate electrodes. Source/drain ion implants are performed with include fluoride ions. The substrate is degassed in an inert atmosphere to remove the excess fluoride ions. A dielectric layer is deposited over the pattern of polycide gate electrodes and flowed. There is no excess fluorine gas concentration to form a bubble in the dielectric layer.