Patents by Inventor Cheng-Te Chu

Cheng-Te Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145132
    Abstract: An over-current protection device includes first and second electrode layers and a PTC material layer laminated therebetween. The PTC material layer includes a polymer matrix, and a conductive filler. The polymer matrix has a fluoropolymer. The total volume of the PTC material layer is calculated as 100%, and the fluoropolymer accounts for 47-62% by volume of the PTC material layer. The fluoropolymer has a melt viscosity higher than 3000 Pa·s.
    Type: Application
    Filed: March 16, 2023
    Publication date: May 2, 2024
    Inventors: CHENG-YU TUNG, CHEN-NAN LIU, Chia-Yuan Lee, HSIU-CHE YEN, YUNG-HSIEN CHANG, Yao-Te Chang, FU-HUA CHU
  • Publication number: 20240145133
    Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a polymer matrix and a first conductive filler. The polymer matrix includes a polyolefin-based polymer and a fluoropolymer. The fluoropolymer has a melt flow index higher than 1.9 g/10 min, and the polyolefin-based polymer and the fluoropolymer together form an interpenetrating polymer network (IPN). The first conductive filler has a metal-ceramic compound dispersed in the polymer matrix.
    Type: Application
    Filed: April 5, 2023
    Publication date: May 2, 2024
    Inventors: CHEN-NAN LIU, YUNG-HSIEN CHANG, CHENG-YU TUNG, HSIU-CHE YEN, Chia-Yuan LEE, Yao-Te CHANG, FU-HUA CHU
  • Publication number: 20240127988
    Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a first polymer and a conductive filler. The first polymer consists of polyvinylidene difluoride (PVDF), and PVDF exists in different phases such as ?-PVDF, ?-PVDF and ?-PVDF. The total amount of ?-PVDF, ?-PVDF and ?-PVDF is calculated as 100%, and the amount of ?-PVDF accounts for 48% to 55%. The conductive filler has a metal-ceramic compound.
    Type: Application
    Filed: March 2, 2023
    Publication date: April 18, 2024
    Inventors: HSIU-CHE YEN, YUNG-HSIEN CHANG, CHENG-YU TUNG, Chia-Yuan Lee, CHEN-NAN LIU, Yao-Te Chang, FU-HUA CHU
  • Publication number: 20240127989
    Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a first polymer and a conductive filler. The first polymer consists of polyvinylidene difluoride (PVDF), and PVDF exists in different phases such as ?-PVDF, ?-PVDF and ?-PVDF. The total amount of ?-PVDF, ?-PVDF and ?-PVDF is calculated as 100%, and the amount of ?-PVDF accounts for 33% to 42%.
    Type: Application
    Filed: January 25, 2023
    Publication date: April 18, 2024
    Inventors: CHIA-YUAN LEE, CHENG-YU TUNG, HSIU-CHE YEN, CHEN-NAN LIU, YUNG-HSIEN CHANG, YAO-TE CHANG, FU-HUA CHU
  • Patent number: 5731243
    Abstract: A method for backside grinding a semiconductor wafer and forming a contamination free bonding pad connection. The method comprises forming a passivation layer over a metal layer. Applying a photoresist pattern with an opening which will define a bonding pad area and removing the passivation layer exposed in the opening. Next, the photoresist is removed, but a polymer residue is often formed on the surfaces of the passivation layer surrounding the bonding pad. In a novel step, the residue is removed using an etchant containing Dimethylsulfoxide (D.M.D.O.) aud Monoethanolamine (M.E.A.) and is followed by au oxygen plasma treatment. Next, the device side of the wafer is covered with a protective tape and the backside of the wafer is grouud back. The tape is removed revealing a contamination free bonding pad area. A bonding connection is then made to the bonding pad.
    Type: Grant
    Filed: September 5, 1995
    Date of Patent: March 24, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-min Peng, Yung-Haw Liaw, Cheng-Te Chu, Hsin-chieh Huang
  • Patent number: 5434096
    Abstract: A method is described for fabricating an integrated circuit with polycide gate electrodes in which there is no delamination of the overlying dielectric layer. A polysilicon layer over a gate dielectric is provided on a silicon substrate. A silicide layer is formed over the polysilicon layer using WF.sub.6 and SiH.sub.4 as the reaction gases. The silicide and polysilicon layers are patterned to form polycide gate electrodes. The substrate is annealed initially in an inert gas atmosphere to remove excess fluorine gas, then in an oxygen atmosphere. Lightly doped source and drain ion implants are performed. Spacers are formed on the sidewalls of the polycide gate electrodes. Source/drain ion implants are performed with include fluoride ions. The substrate is degassed in an inert atmosphere to remove the excess fluoride ions. A dielectric layer is deposited over the pattern of polycide gate electrodes and flowed. There is no excess fluorine gas concentration to form a bubble in the dielectric layer.
    Type: Grant
    Filed: October 5, 1994
    Date of Patent: July 18, 1995
    Assignee: Taiwan Semiconductor Manufacturing Company LTD.
    Inventors: Cheng-Te Chu, Yung-Haw Liaw, Tien C. Chang, Hsin-Chieh Huang