Abstract: A method for DRAM protection comprises allocating address spaces respectively for a first and second common region, a first and second secure region; detecting whether common data has an address within the address spaces for the first secure region; outputting a digital signal remapping an address of the common data to the address space for the second common region if yes; detecting whether secure data has an address within the address spaces for the first common region; outputting a digital signal indicating remapping an address of the secure data to the address space for the second secure region if yes. Alternatively, the method further comprises generating a random key; an updated written data by permuting orders of bits of an original DRAM written data; generating an encrypted data by performing a function on the updated written data with the generated random key; and dynamically updating the generated random key.

Abstract: A method for DRAM protection comprises allocating address spaces respectively for a first and second common region, a first and second secure region; detecting whether common data has an address within the address spaces for the first secure region; outputting a digital signal remapping an address of the common data to the address space for the second common region if yes; detecting whether secure data has an address within the address spaces for the first common region; outputting a digital signal indicating remapping an address of the secure data to the address space for the second secure region if yes. Alternatively, the method further comprises generating a random key; an updated written data by permuting orders of bits of an original DRAM written data; generating an encrypted data by performing a function on the updated written data with the generated random key; and dynamically updating the generated random key.

Abstract: A one-time programmable (OTP) memory device includes a memory array. The memory array includes: a data storage section for storing application data; a verification information section including at least one verification information unit, wherein each verification information unit includes a verification address region for storing verification address information associated with an address of a subject region in the data storage section, and a reference verification data region for storing one or more reference verification data, and wherein each reference verification data is calculated through reference verification calculation on the application data stored in the subject region using a predetermined verification algorithm.

Abstract: A method for DRAM protection comprises allocating address spaces respectively for a first and second common region, a first and second secure region; detecting whether common data has an address within the address spaces for the first secure region; outputting a digital signal remapping an address of the common data to the address space for the second common region if yes; detecting whether secure data has an address within the address spaces for the first common region; outputting a digital signal indicating remapping an address of the secure data to the address space for the second secure region if yes. Alternatively, the method further comprises generating a random key; an updated written data by permuting orders of bits of an original DRAM written data; generating an encrypted data by performing a function on the updated written data with the generated random key; and dynamically updating the generated random key.

Abstract: A one-time programmable (OTP) memory device includes a memory array. The memory array includes: a data storage section for storing application data; a verification information section including at least one verification information unit, wherein each verification information unit includes a verification address region for storing verification address information associated with an address of a subject region in the data storage section, and a reference verification data region for storing one or more reference verification data, and wherein each reference verification data is calculated through reference verification calculation on the application data stored in the subject region using a predetermined verification algorithm.

Abstract: According to a method in the present invention, first whether an inter-frame difference for each pixel in predetermined first region and second region in the dynamic image exceeds a predetermined threshold is judged to determine whether the pixel is a static information point, and when, in the second region, pixels in regions not overlapping with the first region are determined as non-static information points, judgment on the inter-frame difference and the predetermined threshold is stopped; and then static characteristic information in the dynamic image is determined based on the static information points in the first region. Preferably, the inter-frame difference for each pixel in the first region may be re-judged based on an adjusted predetermined threshold, to further determine the static characteristic information in the dynamic image, so that static opaque static characteristic information or static characteristic information with arbitrary degrees of transparency in the dynamic image can be detected.

Abstract: According to a method in the present invention, first whether an inter-frame difference for each pixel in predetermined first region and second region in the dynamic image exceeds a predetermined threshold is judged to determine whether the pixel is a static information point, and when, in the second region, pixels in regions not overlapping with the first region are determined as non-static information points, judgment on the inter-frame difference and the predetermined threshold is stopped; and then static characteristic information in the dynamic image is determined based on the static information points in the first region. Preferably, the inter-frame difference for each pixel in the first region may be re-judged based on an adjusted predetermined threshold, to further determine the static characteristic information in the dynamic image, so that static opaque static characteristic information or static characteristic information with arbitrary degrees of transparency in the dynamic image can be detected.

Abstract: A data de-shuffler includes a buffer having a set of addressable locations for storing data and control circuitry for de-shuffling a sequence of shuffled data samples. The control circuitry stores a first data sample of the sequence of shuffled data samples at a first location in the buffer with a first address generated from an entry in a look up table and stores a second data sample at a second location in the buffer with a second address generated by incrementing from the first address by a selected incrementation value. The first and second locations in the buffer place the first and second samples in corresponding positions in an un-shuffled sequence of samples.

Abstract: Integrated circuit provides single-pass, real-time digital image encoding by digital signal processor for variable bit rate (VBR) control to improve decoded output quality. Possible peak bit rate range for multiple groups of pictures (GOP) and averaged bit rate limit encoded signal bit rate. Possible bit rate range constraint sets upper/lower range, which is pre-specified or dynamically adapted for current and future GOPs. Signal processor calculates perceptual weighting variable at macroblock level for multiple GOPs, nominal quantization parameters for multiple GOPs, quantization parameter associated at picture level, effective bit rate for each GOP, bit allocation for each picture, and total bit allocation for multiple GOPs. Variable rate signal is recordable in DVD or camcorder device.

Abstract: A digital signal processor encodes video signals per MPEG standard to achieve multi-stage, low-complexity motion estimation for interframe video coding. A dual-stage motion prediction module processes a compressed bitstream through pixel-averaging, and then applies a Sum-Of-Absolute-Difference (SOAD) function to the bitstream. A minimum motion vector signal is thereby generated over a search range initially for rough determination, then to provide a more refined estimation, the SOAD function is re-applied to the surrounding 16.times.16 blocks, preferably by full and half-pel vertical and horizontal offsets.

Abstract: A method for coding frames of video wherein a coding circuit (14,16,18) includes a processor (30) for performing an orthogonal transform such as a discretecosine transform and a quantizer (32) for quantizing the resulting transform coefficients. The coding circuit codes the video frames using intra-frame, predictive or interpolative coding to generate code bits at a variable rate. The code bits are stored at a variable rate in a rate buffer (22), which transmits the code bits into a communication channel (24) at a pseudo-constant rate, i.e. a rate which is constant in every time interval of one frame. To maintain the contents of the rate buffer (22) within predetermined limits, the quantization parameters utilized by the quantizer (32) are periodically adjusted to increase or decrease the amount of code bits generated by the coding circuit.

Abstract: An adaptive transform coding algorithm for a still image utilizes a quadtree based variable block size discrete cosine transform to achieve a better tradeoff between bit rate and image quality. The choice of appropriate block size is made according to a mean based decision rule which can discriminate various image contents for better visual quality.

Abstract: In accordance with our adaptive transform coding algorithm for a still image, the image is divided into small blocks of pixels and each block of pixels is transformed using an orthogonal transform such as a discrete cosine transform. The resulting transform coefficients are compressed and coded to form a bit stream for transmission to a remote receiver. The compression parameters for each block of pixels are chosen based on a busyness measure for the block such as the magnitude of the (K+1).sup.th most significant transform coefficient. This enables busy blocks for which the human visual system is not sensitive to degradation to be transmitted at low bit rates while enabling other blocks for which the human visual system is sensitive to degradation to be transmitted at higher bit rates. Thus, the algorithm is able to achieve a tradeoff between image quality and bit rate.

Abstract: A system for compressing and transmitting a digital image signal over a limited bandwidth communication channel, transform codes the image values and quantizes the transform coefficients according to a two-dimensional model of the sensitivity of the human visual system. The model of the human visual system is characterized by being less sensitive to diagonally oriented spatial frequencies than to horizontally or vertically oriented spatial frequencies, thereby achieving increased compression of the image.

Abstract: In a method and apparatus for transmitting a digital image over a limited bandwidth communication channel, an image is block transformed to produce blocks of transform coefficients; the transform coefficients are quantized in accordance with a model of the visibility of quantization error in the presence of image detail; the quantized coefficients are encoded with a minimum redundancy code; and the coded, quantized transform coefficients are transmitted.

Abstract: A still image communication system performs a block cosine transformation on an image of bandwidth compression. A transmitter subsamples a full resolution image, to provide a preview image, and transforms and transmits the preview image prior to transforming and transmitting the full resolution image. A receiver and displays the preview image, and replaces the preview image on the display block-by-block as the full resolution is received.