Patents by Inventor Cheng-Ting Chen

Cheng-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170179083
    Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 22, 2017
    Inventors: Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 9627234
    Abstract: A method and a system that include providing a localized dispensing apparatus. A substrate having a material disposed on its top surface is oriented above the localized dispensing apparatus. A chemical is then dispensed from the localized dispensing apparatus onto the top surface of the oriented substrate. The chemical removes the material. The path for the material removal may be determined and the localized dispensing apparatus programmed to provide chemical according to the path.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Min Huang, Chih-Wei Lin, Cheng-Ting Chen, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20170098571
    Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.
    Type: Application
    Filed: December 15, 2016
    Publication date: April 6, 2017
    Inventors: Ming-Da Cheng, Hsiu-Jen Lin, Cheng-Ting Chen, Wei-Yu Chen, Chien-Wei Lee, Chung-Shi Liu
  • Patent number: 9583464
    Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 9538582
    Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Da Cheng, Hsiu-Jen Lin, Cheng-Ting Chen, Wei-Yu Chen, Chien-Wei Lee, Chung-Shi Liu
  • Publication number: 20160343692
    Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
    Type: Application
    Filed: August 8, 2016
    Publication date: November 24, 2016
    Inventors: Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 9437564
    Abstract: A structure comprises a passivation layer formed over a semiconductor substrate, a connection pad enclosed by the passivation layer, a redistribution layer formed over the passivation layer, wherein the redistribution layer is connected to the connection pad, a bump formed over the redistribution layer, wherein the bump is connected to the redistribution layer and a molding compound layer formed over the redistribution layer. The molding compound layer comprises a flat portion, wherein a bottom portion of the bump is embedded in the flat portion of the molding compound layer and a protruding portion, wherein a middle portion of the bump is surrounded by the protruding portion of the molding compound layer.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: September 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Hsuan-Ting Kuo, Cheng-Ting Chen, Ai-Tee Ang, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9418955
    Abstract: A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Fa Lu, Chung-Shi Liu, Chen-Hua Yu, Wei-Yu Chen, Cheng-Ting Chen
  • Patent number: 9412689
    Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin, Ming-Da Cheng
  • Publication number: 20160218055
    Abstract: The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.
    Type: Application
    Filed: April 6, 2016
    Publication date: July 28, 2016
    Inventors: HSIU-JEN LIN, WEN-HSIUNG LU, CHENG-TING CHEN, HSUAN-TING KUO, WEI-YU CHEN, MING-DA CHENG, CHUNG-SHI LIU
  • Patent number: 9373603
    Abstract: Reflow processes and apparatuses are disclosed. A process includes enclosing a package workpiece in an enclosed environment of a chamber of a reflow tool; causing an oxygen content of the enclosed environment of the chamber to be less than 40 ppm; and performing a reflow process in the enclosed environment of the chamber while the oxygen content is less than 40 ppm. An apparatus includes a reflow chamber, a door to the reflow chamber, an energy source in the reflow chamber, and gas supply equipment coupled to the chamber. The door is operable to enclose an environment in the reflow chamber. The energy source is operable to increase a temperature in the environment in the reflow chamber. The gas supply equipment is operable to provide a gas to the reflow chamber.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ai-Tee Ang, Hsiu-Jen Lin, Cheng-Ting Chen, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9355927
    Abstract: The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: May 31, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsiu-Jen Lin, Wen-Hsiung Lu, Cheng-Ting Chen, Hsuan-Ting Kuo, Wei-Yu Chen, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20160148889
    Abstract: Presented herein are an interconnect and method for forming the same, the method comprising forming an interconnect on a mounting surface of a mounting pad disposed on a first surface of a first substrate, the interconnect comprising a conductive material, optionally solder or metal, the interconnect avoiding the sides of the mounting pad. A molding compound is applied to the first surface of the first substrate and molded around the interconnect to covering at least a lower portion of the interconnect and a second substrate may be mounted on the interconnect. The interconnect may comprise an interconnect material disposed between a first and second substrate and a molding compound disposed on a surface of the first substrate, and exposing a portion of the interconnect. A sidewall of the interconnect material contacts the mounting pad at an angle less than about 30 degrees from a plane perpendicular to the first substrate.
    Type: Application
    Filed: January 29, 2016
    Publication date: May 26, 2016
    Inventors: Cheng-Ting Chen, Wen-Hsiung Lu, Ming-Da Cheng, Chung-Shi Liu, Mirng-Ji Lii
  • Patent number: 9281288
    Abstract: A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chung Lin, Hsiu-Jen Lin, Cheng-Ting Chen, Chun-Cheng Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9263839
    Abstract: Presented herein are an interconnect and method for forming the same, the method comprising forming an interconnect on a mounting surface of a mounting pad disposed on a first surface of a first substrate, the interconnect comprising a conductive material, optionally solder or metal, the interconnect avoiding the sides of the mounting pad. A molding compound is applied to the first surface of the first substrate and molded around the interconnect to covering at least a lower portion of the interconnect and a second substrate may be mounted on the interconnect. The interconnect may comprise an interconnect material disposed between a first and second substrate and a molding compound disposed on a surface of the first substrate, and exposing a portion of the interconnect. A sidewall of the interconnect material contacts the mounting pad at an angle less than about 30 degrees from a plane perpendicular to the first substrate.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ting Chen, Wen-Hsiung Lu, Ming-Da Cheng, Chung-Shi Liu, Mirng-Ji Lii
  • Patent number: 9230935
    Abstract: A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Lin, Hsiu-Jen Lin, Cheng-Ting Chen, Wei-Yu Chen, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20150249062
    Abstract: Reflow processes and apparatuses are disclosed. A process includes enclosing a package workpiece in an enclosed environment of a chamber of a reflow tool; causing an oxygen content of the enclosed environment of the chamber to be less than 40 ppm; and performing a reflow process in the enclosed environment of the chamber while the oxygen content is less than 40 ppm. An apparatus includes a reflow chamber, a door to the reflow chamber, an energy source in the reflow chamber, and gas supply equipment coupled to the chamber. The door is operable to enclose an environment in the reflow chamber. The energy source is operable to increase a temperature in the environment in the reflow chamber. The gas supply equipment is operable to provide a gas to the reflow chamber.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 3, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ai-Tee Ang, Hsiu-Jen Lin, Cheng-Ting Chen, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20150145130
    Abstract: The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.
    Type: Application
    Filed: November 25, 2013
    Publication date: May 28, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: HSIU-JEN LIN, WEN-HSIUNG LU, CHENG-TING CHEN, HSUAN-TING KUO, WEI-YU CHEN, MING-DA CHENG, CHUNG-SHI LIU
  • Publication number: 20150108638
    Abstract: A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate.
    Type: Application
    Filed: December 1, 2014
    Publication date: April 23, 2015
    Inventors: Chun-Cheng Lin, Hsiu-Jen Lin, Cheng-Ting Chen, Wei-Yu Chen, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 8987058
    Abstract: A plurality of macro and micro alignment marks may be formed on a wafer. The macro alignment marks may be formed in pairs at opposite edges of the wafer. The micro alignment marks may be formed to align to streets on the wafer along a first and second direction. A molding compound may be formed on the wafer. The macro alignment marks may be exposed from the molding compound. A pair of the micro alignment marks may be exposed from the molding compound at opposite ends of the streets along the first and the second direction. The wafer may be aligned to a dicing tool using pairs of the macro alignment marks. The dicing tool may be aligned to the streets using pairs of the micro alignment marks. The wafer may be diced using successive pairs of micro alignment marks along the first and second direction.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Peng Tsai, Wen-Hsiung Lu, Cheng-Ting Chen, Hsien-Wei Chen, Ming-Da Cheng, Chung-Shi Liu