Patents by Inventor Cheng-Ting Chung

Cheng-Ting Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210273104
    Abstract: A semiconductor device according to the present disclosure includes a first isolation feature and a second isolation feature, a fin structure extending lengthwise along a first direction and sandwiched between the first isolation feature and the second isolation feature along a second direction perpendicular to the first direction, a first channel member disposed over the first isolation feature, a second channel member disposed over the second isolation feature, and a gate structure disposed over and wrapping around the first channel member and the second channel member.
    Type: Application
    Filed: December 23, 2020
    Publication date: September 2, 2021
    Inventors: Pei-Hsun Wang, Chun-Hsiung Lin, Cheng-Ting Chung, Chih-Hao Wang
  • Publication number: 20210265349
    Abstract: A semiconductor device according to the present disclosure includes a first plurality of gate-all-around (GAA) devices in a first device area and a second plurality of GAA devices in a second device area. Each of the first plurality of GAA devices includes a first vertical stack of channel members extending along a first direction, and a first gate structure over and around the first vertical stack of channel members. Each of the second plurality of GAA devices includes a second vertical stack of channel members extending along a second direction, and a second gate structure over and around the second vertical stack of channel members. Each of the first plurality of GAA devices includes a first channel length and each of the second plurality of GAA devices includes a second channel length smaller than the first channel length.
    Type: Application
    Filed: February 26, 2020
    Publication date: August 26, 2021
    Inventors: Cheng-Ting Chung, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11088255
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first gate-all-around (GAA) transistor over a first region of a substrate and a second GAA transistor over a second region of the substrate. The first GAA transistor includes a plurality of first channel members stacked along a first direction vertical to a top surface of the substrate and a first gate structure over the plurality of first channel members. The second GAA transistor includes a plurality of second channel members stacked along a second direction parallel to the top surface of the substrate and a second gate structure over the plurality of second channel members. The plurality of first channel members and the plurality of second channel members comprise a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane. The first direction is normal to the first crystal plane and the second direction is normal to the second crystal plane.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ting Chung, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11088251
    Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed on opposite sides of a plurality of conductive layers. A dielectric layer overlies the first source/drain region, the second source/drain region, and the plurality of conductive layers. An electrical contact extends through the dielectric layer and the first source/drain region, where a first surface of the electrical contact is a surface of the electrical contact that is closest to the substrate, a first surface of the plurality of conductive layers is a surface of the plurality of conductive layers that is closest to the substrate, and the first surface of the electrical contact is closer to the substrate than the first surface of the plurality of conductive layers.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wei Tsai, Yi-Bo Liao, Cheng-Ting Chung, Yu-Xuan Huang, Kuan-Lun Cheng
  • Patent number: 11088256
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first gate-all-around (GAA) transistor over a first region of a substrate and a second GAA transistor over a second region of the substrate. The first GAA transistor includes a plurality of first channel members stacked along a first direction vertical to a top surface of the substrate and a first gate structure over the plurality of first channel members. The second GAA transistor includes a plurality of second channel members stacked along a second direction parallel to the top surface of the substrate and a second gate structure over the plurality of second channel members. The plurality of first channel members and the plurality of second channel members comprise a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane. The first direction is normal to the first crystal plane and the second direction is normal to the second crystal plane.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ting Chung, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20210202385
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source/drain feature formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact feature interposed between the backside power rail and the first source/drain feature, and electrically connecting the backside power rail to the first source/drain feature. The backside contact feature further includes a first silicide layer on the back side of the substrate.
    Type: Application
    Filed: July 30, 2020
    Publication date: July 1, 2021
    Inventors: Yu-Xuan Huang, Ching-Wei Tsai, Cheng-Ting Chung, Cheng-Chi Chuang, Shang-Wen Chang
  • Publication number: 20210134718
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.
    Type: Application
    Filed: March 27, 2020
    Publication date: May 6, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Bo LIAO, Wei Ju Lee, Cheng-Ting Chung, Hou-Yu Chen, Chun-Fu Cheng, Kuan-Lun Cheng
  • Publication number: 20210098634
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a fin substrate having a first dopant concentration; an anti-punch through (APT) layer disposed over the fin substrate, wherein the APT layer has a second dopant concentration that is greater than the first dopant concentration; a nanostructure including semiconductor layers disposed over the APT layer; a gate structure disposed over the nanostructure and wrapping each of the semiconductor layers, wherein the gate structure includes a gate dielectric and a gate electrode; a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature disposed over the APT layer, wherein the gate structure is disposed between the first epitaxial S/D feature and the second epitaxial S/D feature; and an isolation layer disposed between the APT layer and the fin substrate, wherein a material of the isolation layer is the same as a material of the gate dielectric.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 1, 2021
    Inventors: Cheng-Ting Chung, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20210098588
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 1, 2021
    Inventors: Cheng-Ting Chung, Yi-Bo Liao, Hou-Yu Chen, Kuan-Lun Cheng
  • Publication number: 20210098583
    Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed on opposite sides of a plurality of conductive layers. A dielectric layer overlies the first source/drain region, the second source/drain region, and the plurality of conductive layers. An electrical contact extends through the dielectric layer and the first source/drain region, where a first surface of the electrical contact is a surface of the electrical contact that is closest to the substrate, a first surface of the plurality of conductive layers is a surface of the plurality of conductive layers that is closest to the substrate, and the first surface of the electrical contact is closer to the substrate than the first surface of the plurality of conductive layers.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 1, 2021
    Inventors: Ching-Wei Tsai, Yi-Bo Liao, Cheng-Ting Chung, Yu-Xuan Huang, Kuan-Lun Cheng
  • Publication number: 20210082803
    Abstract: Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Pei-Yu Wang, Cheng-Ting Chung, Wei Ju Lee
  • Patent number: 10879379
    Abstract: Multi-gate semiconductor devices and methods for forming thereof including forming air gaps between the gate and the adjacent source/drain features. A first fin element including a plurality of silicon layers is disposed on a substrate, a first gate structure is formed over a channel region of the first fin element. An air gap is formed such that it is disposed on a sidewall of the portion of the first gate structure. An epitaxial source/drain feature abuts the air gap. A portion of the first gate structure may also be disposed between first and second layers of the plurality of silicon layers.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ting Chung, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20200381531
    Abstract: Multi-gate semiconductor devices and methods for forming thereof including forming air gaps between the gate and the adjacent source/drain features. A first fin element including a plurality of silicon layers is disposed on a substrate, a first gate structure is formed over a channel region of the first fin element. An air gap is formed such that it is disposed on a sidewall of the portion of the first gate structure. An epitaxial source/drain feature abuts the air gap. A portion of the first gate structure may also be disposed between first and second layers of the plurality of silicon layers.
    Type: Application
    Filed: October 11, 2019
    Publication date: December 3, 2020
    Inventors: Cheng-Ting CHUNG, Ching-Wei TSAI, Kuan-Lun CHENG
  • Publication number: 20200381530
    Abstract: Multi-gate semiconductor devices and methods for forming thereof including forming air gaps between the gate and the adjacent source/drain features. A first fin element including a plurality of silicon layers is disposed on a substrate, a first gate structure is formed over a channel region of the first fin element. An air gap is formed such that it is disposed on a sidewall of the portion of the first gate structure. An epitaxial source/drain feature abuts the air gap. A portion of the first gate structure may also be disposed between first and second layers of the plurality of silicon layers.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 3, 2020
    Inventors: Cheng-Ting CHUNG, Ching-Wei TSAI, Kuan-Lun CHENG
  • Publication number: 20200365703
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first gate-all-around (GAA) transistor over a first region of a substrate and a second GAA transistor over a second region of the substrate. The first GAA transistor includes a plurality of first channel members stacked along a first direction vertical to a top surface of the substrate and a first gate structure over the plurality of first channel members. The second GAA transistor includes a plurality of second channel members stacked along a second direction parallel to the top surface of the substrate and a second gate structure over the plurality of second channel members. The plurality of first channel members and the plurality of second channel members comprise a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane. The first direction is normal to the first crystal plane and the second direction is normal to the second crystal plane.
    Type: Application
    Filed: May 17, 2019
    Publication date: November 19, 2020
    Inventors: Cheng-Ting Chung, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20200365704
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first gate-all-around (GAA) transistor over a first region of a substrate and a second GAA transistor over a second region of the substrate. The first GAA transistor includes a plurality of first channel members stacked along a first direction vertical to a top surface of the substrate and a first gate structure over the plurality of first channel members. The second GAA transistor includes a plurality of second channel members stacked along a second direction parallel to the top surface of the substrate and a second gate structure over the plurality of second channel members. The plurality of first channel members and the plurality of second channel members comprise a semiconductor material having a first crystal plane and a second crystal plane different from the first crystal plane. The first direction is normal to the first crystal plane and the second direction is normal to the second crystal plane.
    Type: Application
    Filed: October 30, 2019
    Publication date: November 19, 2020
    Inventors: Cheng-Ting Chung, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 10790280
    Abstract: A semiconductor includes a first transistor and a second transistor. The first transistor includes a first and a second epitaxial layer, formed of a first semiconductor material. The second epitaxial layer is disposed over the first epitaxial layer. The first transistor also includes a first gate dielectric layer surrounds the first and second epitaxial layers and extends from a top surface of the first epitaxial layer to a bottom surface of the second epitaxial layer and a first metal gate layer surrounding the first gate dielectric layer. The second transistor includes a third epitaxial layer formed of the first semiconductor material and a fourth epitaxial layer disposed directly on the third epitaxial layer and formed of a second semiconductor. The second transistor also includes a second gate dielectric layer disposed over the third and fourth epitaxial layers and a second metal gate layer disposed over the second gate dielectric layer.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Chung-Cheng Wu, Ching-Fang Huang, Wen-Hsing Hsieh, Ying-Keung Leung, Cheng-Ting Chung
  • Publication number: 20200135572
    Abstract: A method for fabricating a semiconductor device having a dielectric footing region includes forming a plurality of fin elements extending from a substrate. In some embodiments, a dielectric layer is deposited over each of the plurality of fin elements. After depositing the dielectric layer, a dummy gate electrode is formed over the plurality of fin elements and over the dielectric layer. In some examples, and after forming the dummy gate electrode, a first spacer layer is formed on opposing sidewalls of the dummy gate electrode and over the dielectric layer. In various embodiments, the dielectric layer extends laterally beneath the first spacer layer on each of the opposing sidewalls of the dummy gate electrode to provide the dielectric footing region.
    Type: Application
    Filed: June 21, 2019
    Publication date: April 30, 2020
    Inventors: Cheng-Ting CHUNG, Ching-Wei TSAI, Kuan-Lun CHENG
  • Publication number: 20180175036
    Abstract: A semiconductor includes a first transistor and a second transistor. The first transistor includes a first and a second epitaxial layer, formed of a first semiconductor material. The second epitaxial layer is disposed over the first epitaxial layer. The first transistor also includes a first gate dielectric layer surrounds the first and second epitaxial layers and extends from a top surface of the first epitaxial layer to a bottom surface of the second epitaxial layer and a first metal gate layer surrounding the first gate dielectric layer. The second transistor includes a third epitaxial layer formed of the first semiconductor material and a fourth epitaxial layer disposed directly on the third epitaxial layer and formed of a second semiconductor. The second transistor also includes a second gate dielectric layer disposed over the third and fourth epitaxial layers and a second metal gate layer disposed over the second gate dielectric layer.
    Type: Application
    Filed: February 2, 2018
    Publication date: June 21, 2018
    Inventors: Kuo-Cheng Ching, Chung-Cheng Wu, Ching-Fang Huang, Wen-Hsing Hsieh, Ying-Keung Leung, Cheng-Ting Chung
  • Patent number: 9899387
    Abstract: A semiconductor includes a first transistor and a second transistor. The first transistor includes a first and a second epitaxial layer, formed of a first semiconductor material. The second epitaxial layer is disposed over the first epitaxial layer. The first transistor also includes a first gate dielectric layer surrounds the first and second epitaxial layers and extends from a top surface of the first epitaxial layer to a bottom surface of the second epitaxial layer and a first metal gate layer surrounding the first gate dielectric layer. The second transistor includes a third epitaxial layer formed of the first semiconductor material and a fourth epitaxial layer disposed directly on the third epitaxial layer and formed of a second semiconductor. The second transistor also includes a second gate dielectric layer disposed over the third and fourth epitaxial layers and a second metal gate layer disposed over the second gate dielectric layer.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: February 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Chung-Cheng Wu, Ching-Fang Huang, Wen-Hsing Hsieh, Ying-Keung Leung, Cheng-Ting Chung