Patents by Inventor Cheng-Tse Chen

Cheng-Tse Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240139337
    Abstract: The present disclosure relates to a method for treating a cancer and/or cancer metastasis in a subject comprising administering to the subject irinotecan loaded in a mesoporous silica nanoparticle. The present disclosure also provides a conjugate comprising an agent loaded in a mesoporous silica nanoparticle (MSN) defining at least one pore and having at least one functional group on a sidewall of the at least one pore.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 2, 2024
    Inventors: Cheng-Hsun WU, SI-HAN WU, YI-PING CHEN, RONG-LIN ZHANG, CHUNG-YUAN MOU, Yu-Tse LEE
  • Publication number: 20240095168
    Abstract: A computing system performs shared cache allocation to allocate cache resources to groups of tasks. The computing system monitors the bandwidth at a memory hierarchy device that is at a next level to the cache in a memory hierarchy of the computing system. The computing system estimates a change in dynamic power from a corresponding change in the bandwidth before and after the cache resources are allocated. The allocation of the cache resources are adjusted according to an allocation policy that receives inputs including the estimated change in the dynamic power and a performance indication of task execution.
    Type: Application
    Filed: August 17, 2023
    Publication date: March 21, 2024
    Inventors: Yu-Pin Chen, Jia-Ming Chen, Chien-Yuan Lai, Ya Ting Chang, Cheng-Tse Chen
  • Publication number: 20240095177
    Abstract: A computing system performs partial cache deactivation. The computing system estimates the leakage power of a cache based on operating conditions of the cache including voltage and temperature. The computing system further identifies a region of the cache as a candidate for deactivation based on cache hit counts. The computing system then adjusts the size of the region for the deactivation based on the leakage power and a bandwidth of a memory hierarchy device. The memory hierarchy device is at the next level to the cache in a memory hierarchy of the computing system.
    Type: Application
    Filed: August 17, 2023
    Publication date: March 21, 2024
    Inventors: Yu-Pin Chen, Jia-Ming Chen, Chien-Yuan Lai, Ya Ting Chang, Cheng-Tse Chen