Patents by Inventor Cheng-Tsung Ku
Cheng-Tsung Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11368146Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.Type: GrantFiled: April 14, 2020Date of Patent: June 21, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Yuan Wu, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Cheng-Yang Tsai, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Yu-Lin Chen
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Patent number: 11348847Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.Type: GrantFiled: January 16, 2019Date of Patent: May 31, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Yuan Wu, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Cheng-Yang Tsai, Yu-Lin Chen
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Publication number: 20210288634Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.Type: ApplicationFiled: April 14, 2020Publication date: September 16, 2021Inventors: Kun-Yuan Wu, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Cheng-Yang Tsai, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Yu-Lin Chen
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Publication number: 20200194321Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.Type: ApplicationFiled: January 16, 2019Publication date: June 18, 2020Applicant: United Microelectronics Corp.Inventors: KUN-YUAN WU, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Cheng-Yang Tsai, Yu-Lin Chen
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Patent number: 10319709Abstract: The present invention provides an integrated circuit with a standard cell of an inverter standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.Type: GrantFiled: May 24, 2018Date of Patent: June 11, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chen-Hsien Hsu, Chien-Fu Chen, Cheng-Yang Tsai, Wei-Jen Wang, Chao-Wei Lin, Zhi-Hong Huang, Cheng-Tsung Ku, Chin-Sheng Yang
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Patent number: 10262982Abstract: The present invention provides an integrated circuit with a standard cell of an inverter. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.Type: GrantFiled: October 17, 2017Date of Patent: April 16, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chen-Hsien Hsu, Chien-Fu Chen, Cheng-Yang Tsai, Wei-Jen Wang, Chao-Wei Lin, Zhi-Hong Huang, Cheng-Tsung Ku, Chin-Sheng Yang
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Publication number: 20190088638Abstract: The present invention provides an integrated circuit with a standard cell of an inverter. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.Type: ApplicationFiled: October 17, 2017Publication date: March 21, 2019Inventors: Chen-Hsien Hsu, Chien-Fu Chen, Cheng-Yang Tsai, Wei-Jen Wang, Chao-Wei Lin, Zhi-Hong Huang, Cheng-Tsung Ku, Chin-Sheng Yang
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Publication number: 20190088639Abstract: The present invention provides an integrated circuit with a standard cell of an inverter standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.Type: ApplicationFiled: May 24, 2018Publication date: March 21, 2019Inventors: Chen-Hsien Hsu, Chien-Fu Chen, Cheng-Yang Tsai, Wei-Jen Wang, Chao-Wei Lin, Zhi-Hong Huang, Cheng-Tsung Ku, Chin-Sheng Yang
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Patent number: 10090289Abstract: The present invention provides an integrated circuit with a dummy standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Plural sets of short contact plug and long contact plug disposed between the first dummy gate, the second dummy gate and the gate structures; a doping region overlaps with the long contact plugs; a gate contact plug disposed on the gate structures; plural contact plugs disposed on and electrical contact the long contact plugs; A metal layer includes the first metal line, the second metal line.Type: GrantFiled: November 15, 2017Date of Patent: October 2, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chen-Hsien Hsu, Chien-Fu Chen, Cheng-Yang Tsai, Wei-Jen Wang, Chao-Wei Lin, Zhi-Hong Huang, Cheng-Tsung Ku, Chin-Sheng Yang