Abstract: A method for fabricating a semiconductor structure includes the following steps. Decomposing a layout to first connection patterns and second connection patterns alternatively arranged with each other, where a to-be-split pattern is disposed between the first connection pattern and the second connection pattern; splitting the to-be-split pattern into a cutting portion and a counterpart cutting portion; forming a first photomask having a layout constructed by the first connection pattern and the cutting portion; forming a second photomask having a layout constructed by the second connection pattern and the counterpart cutting portion; transferring layouts of the first and second photomasks to a target layer to form connection patterns and a merged pattern, where the contour of the merged pattern is defined by the cutting portion and the counterpart cutting portion, and each end surface of the merged pattern comprises a recessed region and a protruded region.

Abstract: A semiconductor structure is provided in the present invention, including a substrate with multiple recesses and active areas, multiple bit lines spaced apart in a first direction on the cell region and extending in a second direction perpendicular to the first direction, and the bit line is electrically connected to an active area in the substrate through the recess, and a dummy bit line at an outermost side of the multiple bit lines in the first direction and extending in the second direction, wherein a width of the dummy bit line in the first direction is larger than a width of the bit line in the first direction, and the bit lines and the dummy bit line have the same composition and layer structures.

Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

Abstract: Contacts to n-type and p-type source/drain regions of field-effect transistors comprise a doped contact metal layer positioned between the fill metal and the source/drain regions. The doped contact metal layer comprises a metal and a semiconductor dopant and is formed by reactive sputtering. By varying the concentration of a reactive gas comprising the dopant in the sputtering environment, the atomic composition of the dopant in the doped contact metal layer can vary as the doped contact metal layer is formed. The presence of doped contact metal layers in source/drain contacts can provide for thermally stable low resistance source/drain contacts by inhibiting dopant diffusion from the source/drain regions to the contact metal. In some embodiments, a non-doped contact metal layer can be positioned between the fill metal and the doped contact metal layer.

Abstract: Prosthetic heart valve assemblies and methods, apparatus, and systems used to deliver a prosthetic heart valve assembly. A prosthetic heart valve assembly includes an inner frame, a prosthetic leaflet section disposed within the inner frame extending between in inflow row of cells and an outflow row of cells of the inner frame, and an outer support stent. The inner frame is disposed within the outer support stent, and the outer support stent is coupled and/or fastened to the inner frame. The outer support stent includes a plurality leaflet capturing arms for capturing native leaflets between the leaflet capturing arms and a portion of the prosthetic heart valve assembly when the prosthetic heart valve assembly is implanted in a native valve. For example, the native leaflets can be frictionally secured between the leaflet capturing arms of the support stent and the inner frame.

Abstract: Contacts to n-type and p-type source/drain regions in complementary metal-oxide semiconductor (CMOS) technologies comprise a diffusion barrier layer positioned between the contact metal and the source/drain regions. The contact metal-diffusion barrier layer pairs used to contact n-type and p-type source/drain regions can comprise different materials. The contact metal layers used in n-type and p-type source/drain contacts can comprise the same or different materials. The presence of diffusion barrier layers can provide for thermally stable low resistance source/drain contacts by inhibiting dopant diffusion from the source/drain regions to the contact metal.

Abstract: A semiconductor memory device including an array region and a peripheral region surrounding the array region. The array region includes a plurality of active regions and a first insulating layer disposed between the active regions. The peripheral region includes a peripheral structure, a second insulating layer surrounding the peripheral structure, and a third insulating layer surrounding the second insulating layer. At least a buried word line extends through the array region and the peripheral region, wherein a portion of the buried word line through the second insulating layer comprises a neck profile from a plan view.

Abstract: A DRAM includes a substrate, a plurality of first active regions disposed on the substrate and arranged end-to-end along the first direction, and a plurality of second active regions disposed between the first active regions and arranged end-to-end along the first direction. The second active regions respectively have a first sidewall adjacent to a first trench between the second active region and one of the first active regions and a second sidewall adjacent to a second trench between the ends of the first active regions, wherein the second sidewall is taper than the first sidewall in a cross-sectional view.

Abstract: Prosthetic heart valve assemblies and methods, apparatus, and systems used to deliver a prosthetic heart valve assembly. A prosthetic heart valve assembly includes an inner frame, a prosthetic leaflet section disposed within the inner frame extending between in inflow row of cells and an outflow row of cells of the inner frame, and an outer support stent. The inner frame is disposed within the outer support stent, and the outer support stent is coupled and/or fastened to the inner frame. The outer support stent includes a plurality leaflet capturing arms for capturing native leaflets between the leaflet capturing arms and a portion of the prosthetic heart valve assembly when the prosthetic heart valve assembly is implanted in a native valve. For example, the native leaflets can be frictionally secured between the leaflet capturing arms of the support stent and the inner frame.

Abstract: A semiconductor device includes a substrate, a plurality of bit lines, an insulating layer and a plurality of plugs. The substrate includes a plurality of active areas. The bit lines are separated from each other and disposed on the substrate. The insulating layer overlies a top surface of the substrate. The plugs are disposed on the top surface of the insulating layer and separated from the active areas. The plugs and the bit lines are alternately arranged along a first direction, and the plugs include a plurality of first plugs and at least one second plug. Accordingly, structural defects possibly occurring in a semiconductor device can be effectively ameliorated, so as to form a semiconductor device with improved reliability of components.

Abstract: The present disclosure is directed to a high-voltage magnetron sputtering tool with an enhanced power source including a vacuum chamber containing a magnetron cathode with a magnet array, a target, and an anode, as well as the enhanced power source that includes high-power DC power source and controller that produces a pulsed output. In an aspect, the enhanced power source may include a standard power source that is retrofitted a supplemental high-power DC power source and controller, and alternatively, a high-power DC power source and controller that replaces the standard power source. In addition, the present disclosure is directed to methods for depositing a hydrogen-free diamond-like carbon film on a semiconductor substrate using the high-voltage magnetron sputtering tool. In an aspect, the hydrogen-free diamond-like carbon film may be an etch mask having a sp3 carbon bonding that is greater than 60 percent.

Abstract: Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.

Abstract: A semiconductor device includes a substrate; at least one trench located at a top surface of the substrate; and a first dielectric layer, a second dielectric layer and a third dielectric layer that are sequentially stacked on an inner wall of each of the at least one trench. A topmost surface of the first dielectric layer is lower than a topmost surface of the second dielectric layer and the top surface of the substrate, to form a first groove between the second dielectric layer and the substrate. An edge corner between the top surface of the substrate and the inner wall of each of the at least one trench is in a shape of a fillet curve. The fillet structure is smooth and round without a sharp corner, reducing point discharge and improving reliability of the shallow trench isolation structure.

Abstract: A memory device includes a first memory cell, a second memory cell, a word line, a bit line, a first source line and a second source line. The first memory cell includes a control terminal, a data terminal and a source terminal. The first memory cell includes a control terminal, a data terminal and a source terminal. The word line is coupled to the control terminal of the first memory cell and the control terminal of the second memory cell. The bit line is coupled to the data terminal of the first memory cell and the data terminal of the second memory cell. The first source line is coupled to the source terminal of the first memory cell for receiving a first source voltage. The second source line is coupled to the source terminal of the second memory cell for receiving a second source voltage.

Abstract: The present disclosure relates to a semiconductor device and a method of fabricating the same, the semiconductor device including a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate, including a plurality of first active fragments and a plurality of second active fragments. The first active fragments and the second active fragments are parallel and separately extended along a first direction, and the second active fragments are disposed outside all of the first active fragments. The first active fragments have a same length in the first direction, being a first length, the second active fragment have a second length in the first direction, and the second length is greater than the first length.

Abstract: Prosthetic heart valve assemblies and methods, apparatus, and systems used to deliver a prosthetic heart valve assembly. A prosthetic heart valve assembly includes an inner frame, a prosthetic leaflet section disposed within the inner frame extending between in inflow row of cells and an outflow row of cells of the inner frame, and an outer support stent. The inner frame is disposed within the outer support stent, and the outer support stent is coupled and/or fastened to the inner frame. The outer support stent includes a plurality leaflet capturing arms for capturing native leaflets between the leaflet capturing arms and a portion of the prosthetic heart valve assembly when the prosthetic heart valve assembly is implanted in a native valve. For example, the native leaflets can be frictionally secured between the leaflet capturing arms of the support stent and the inner frame.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a plurality of gate conductive patterns on the substrate; an interlayer dielectric layer covering the gate conductive patterns on the substrate; an interconnect structure comprising a contact plug and a first contact pad, the contact plug extending through the interlayer dielectric layer to the substrate, the first contact pad fully covering a top of the contact plug and extending laterally over part of a top surface of the interlayer dielectric layer; and a second contact pad formed on the top surface of the interlayer dielectric layer and spaced apart from a side edge of the first contact pad, wherein the second contact pad is formed and fully overlays on the interlayer dielectric layer and an isolation plug is spaced apart from the first contact pad.

Abstract: A power transistor conversion device comprising: a base frame; and a fixing frame; wherein the base frame is provided with two limit holes within the base frame for fixing the base frame, and two through holes through which an input pin and an output pin of the power transistor pass through the base frame; the fixing frame is located perpendicular to an upper surface of the base frame, and the fixing frame is fastened to the base frame; the fixing frame is provided with a transistor limit unit for fixing the power transistor on the fixing frame. When applied, the transistor or the power transistor is fixed on the power transistor conversion device through the transistor limit unit, and then directly replaces the position of the power transistor to achieve better replaceability and better heat dissipation.

Abstract: Low leakage thin film capacitors for decoupling, power delivery, integrated circuits, related systems, and methods of fabrication are disclosed. Such thin film capacitors include a titanium dioxide dielectric and one or more noble metal oxide electrodes. Such thin film capacitors are suitable for high voltage applications and provide low current density leakage.

Abstract: The present disclosure relates to a semiconductor memory device and a fabricating method thereof, and the semiconductor memory device includes a substrate, bit lines, plugs and a spacer structure. The bit lines are separately disposed on the substrate, and the plugs are also disposed on the substrate to alternately arrange with the bit lines. The spacer structure is disposed on the substrate, between each of the bit lines and each of the plugs. The spacer structure includes a first air gap layer, a first spacer and a second air gap layer, and the first air gap layer, the first spacer and the second air gap layer are sequentially stacked between sidewalls of the bit lines and the plugs. Therefore, two air gap layers may be formed between the bit lines and the storage node contacts to improve the delay between the resistor and the capacitor.