Patents by Inventor Cheng-Tung Wang

Cheng-Tung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12130763
    Abstract: A storage enclosure connected to a server via an external network and includes a network switch, an expander that is connected to the network switch and that is configured to generate enclosure data that supports a format conforming with SCSI Enclosure Services, and a board management controller (BMC) that is connected to the network switch and the expander. The BMC is configured to translate the enclosure data into enclosure translating data that supports a Redfish® format. The expander is configured to, after generating the enclosure data, transmit the enclosure data through the network switch to the BMC via an internal network. The BMC is configured to translate the enclosure data into the enclosure translating data, and to transmit the enclosure translating data to the network switch. The network switch transmits the enclosure translating data to the server through the external network.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: October 29, 2024
    Assignee: MITAC COMPUTING TECHNOLOGY CORPORATION
    Inventors: Jyun-Jie Wang, Shao-Che Chang, Cheng-Tung Wang, Yen-Lun Tseng, Chin-Hung Tan
  • Publication number: 20230195671
    Abstract: A storage enclosure connected to a server via an external network and includes a network switch, an expander that is connected to the network switch and that is configured to generate enclosure data that supports a format conforming with SCSI Enclosure Services, and a board management controller (BMC) that is connected to the network switch and the expander. The BMC is configured to translate the enclosure data into enclosure translating data that supports a Redfish® format. The expander is configured to, after generating the enclosure data, transmit the enclosure data through the network switch to the BMC via an internal network. The BMC is configured to translate the enclosure data into the enclosure translating data, and to transmit the enclosure translating data to the network switch. The network switch transmits the enclosure translating data to the server through the external network.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 22, 2023
    Inventors: Jyun-Jie WANG, Shao-Che CHANG, Cheng-Tung WANG, Yen-Lun TSENG, Chin-Hung TAN
  • Patent number: 11513697
    Abstract: A control system for a storage apparatus includes two input/output modules (IOMs), and two non-volatile memory (NVM) devices that are electrically connected to the IOMs, respectively, and that each store a firmware code. Each of the IOMs is configured to execute a firmware corresponding to the firmware code stored in the corresponding NVM device, and to enter an active mode or a passive mode after executing the firmware. The IOMs are configured such that when one IOM operating in the passive mode detects abnormal operation of the other IOM operating in the active mode, the one IOM sends, to the other IOM, the firmware code stored in the NVM device electrically connected to the one IOM, in order to update the firmware code in the NVM device electrically connected to the other IOM.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: November 29, 2022
    Assignee: MITAC COMPUTING TECHNOLOGY CORPORATION
    Inventors: Jyun-Jie Wang, Cheng-Tung Wang, Yen-Lun Tseng
  • Publication number: 20220075533
    Abstract: A control system for a storage apparatus includes two input/output modules (IOMs), and two non-volatile memory (NVM) devices that are electrically connected to the IOMs, respectively, and that each store a firmware code. Each of the IOMs is configured to execute a firmware corresponding to the firmware code stored in the corresponding NVM device, and to enter an active mode or a passive mode after executing the firmware. The IOMs are configured such that when one IOM operating in the passive mode detects abnormal operation of the other IOM operating in the active mode, the one IOM sends, to the other IOM, the firmware code stored in the NVM device electrically connected to the one IOM, in order to update the firmware code in the NVM device electrically connected to the other IOM.
    Type: Application
    Filed: September 3, 2021
    Publication date: March 10, 2022
    Inventors: Jyun-Jie WANG, Cheng-Tung WANG, Yen-Lun TSENG
  • Patent number: 10942555
    Abstract: A power supplying method for a computer system is proposed. The computer system includes a first computer node, a first power supply unit corresponding to the first computer node, a second computer node, a second power supply unit corresponding to the second computer node, and a connection module electrically connected to the computer nodes and the power supply units. The power supplying method includes: detecting, by the first computer node, whether the second power supply unit operates abnormally; and upon detecting at least that the second power supply unit operates abnormally, controlling, by the first computer node, the first power supply unit to provide electric power to the second computer node through the connection module.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: March 9, 2021
    Assignee: Mitac Computing Technology Corporation
    Inventors: Ming-Li Tsai, Jyun-Jie Wang, Cheng-Tung Wang, Chia-Ming Liu, Ming-Hsuan Tsai
  • Publication number: 20190121413
    Abstract: A power supplying method for a computer system is proposed. The computer system includes a first computer node, a first power supply unit corresponding to the first computer node, a second computer node, a second power supply unit corresponding to the second computer node, and a connection module electrically connected to the computer nodes and the power supply units. The power supplying method includes: detecting, by the first computer node, whether the second power supply unit operates abnormally; and upon detecting at least that the second power supply unit operates abnormally, controlling, by the first computer node, the first power supply unit to provide electric power to the second computer node through the connection module.
    Type: Application
    Filed: October 18, 2018
    Publication date: April 25, 2019
    Inventors: Ming-Li TSAI, Jyun-Jie WANG, Cheng-Tung WANG, Chia-Ming LIU, Ming-Hsuan TSAI
  • Patent number: 6891495
    Abstract: An analog-to-digital converter including analog-to-digital converting units connected in serial. The current comparator includes a current input terminal to receive a sampling current, a reference current input terminal to receive a reference current and a bit output terminal for outputting a bit signal. The current operation circuit includes a current output terminal for outputting a compared current according to the sampling current and the reference current. The operation controlling terminal selects the compared current according to the bit signal. The controlling terminal receives a clock signal to latch the bit signal. The analog-to-digital converting units output the bit signals in sequence in a period of the clock signal.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: May 10, 2005
    Assignee: Endpoints Technology Corporation
    Inventors: Jiann-Jong Chen, Po-Jen Huang, Hung-Yih Lin, Cheng-Tung Wang
  • Publication number: 20040080446
    Abstract: An analog-to-digital converter including analog-to-digital converting units connected in serial. The current comparator includes a current input terminal to receive a sampling current, a reference current input terminal to receive a reference current and a bit output terminal for outputting a bit signal. The current operation circuit includes a current output terminal for outputting a compared current according to the sampling current and the reference current. The operation controlling terminal selects the compared current according to the bit signal. The controlling terminal receives a clock signal to latch the bit signal. The analog-to-digital converting units output the bit signals in sequence in a period of the clock signal.
    Type: Application
    Filed: June 2, 2003
    Publication date: April 29, 2004
    Applicant: EndPoints Technology Corporation
    Inventors: Jiann-Jong Chen, Po-Jen Huang, Hung-Yih Lin, Cheng-Tung Wang