Patents by Inventor Cheng-Tzu Yang
Cheng-Tzu Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240097011Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITEDInventors: Han-Yu LIN, Fang-Wei LEE, Kai-Tak LAM, Raghunath PUTIKAM, Tzer-Min SHEN, Li-Te LIN, Pinyen LIN, Cheng-Tzu YANG, Tzu-Li LEE, Tze-Chung LIN
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Patent number: 11855192Abstract: A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.Type: GrantFiled: January 19, 2021Date of Patent: December 26, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITEDInventors: Han-Yu Lin, Fang-Wei Lee, Kai-Tak Lam, Raghunath Putikam, Tzer-Min Shen, Li-Te Lin, Pinyen Lin, Cheng-Tzu Yang, Tzu-Li Lee, Tze-Chung Lin
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Publication number: 20220173224Abstract: A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.Type: ApplicationFiled: January 19, 2021Publication date: June 2, 2022Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company LimitedInventors: Han-Yu LIN, Fang-Wei LEE, Kai-Tak LAM, Raghunath PUTIKAM, Tzer-Min SHEN, Li-Te LIN, Pinyen LIN, Cheng-Tzu YANG, Tzu-Li LEE, Tze-Chung LIN
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Patent number: 7785941Abstract: A method for fabricating a thin film transistor (TFT) is provided. A substrate having a gate, a dielectric layer, a channel layer and an ohmic contact layer formed thereon is provided. Next, a metal layer is formed over the substrate covering the ohmic contact layer. Next, the metal layer and the ohmic contact layer are simultaneously etched by a wet etching process to form a source/drain and expose the channel layer. Because the wet etching process can be used to selectively etch the ohmic contact layer, damage to the underlying channel layer may be negligible. Thus, the reliability of the device may be promoted. Furthermore, the process may be simplified, the production yield and the throughput of TFT may be increased.Type: GrantFiled: December 11, 2007Date of Patent: August 31, 2010Assignees: Taiwan TFT LCD Association, Chunghwa Picture Tubes, Ltd., Au Optronics Corporation, Hannstar Display Corporation, Chi Mei Optoelectronics Corporation, Industrial Technology Research Institute, TPO Display Corp.Inventors: Sai-Chang Liu, Cheng-Tzu Yang, Chien-Wei Wu
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Patent number: 7566404Abstract: An etchant for patterning composite layer containing copper is provided. The etchant includes peracetic acid being about 5% to 40% by weight and serving as a major component, a peracetic acid stabilizer being about 5% to 15% by weight, an organic acid being about 5% to 10% by weight, an inorganic acid being about 5% to 15% by weight, a salt being about 8% to 15% by weight, which are based on the total weight of the etchant.Type: GrantFiled: February 2, 2007Date of Patent: July 28, 2009Assignees: Taiwan TFT LCD Association, Chunghwa Picture Tubes, Ltd., Au Optronics Corporation, Hannstar Display Corporation, Chi Mei Optoelectronics Corporation, Industrial Technology Research Institute, TPO Display Corp.Inventors: Sai-Chang Liu, Cheng-Tzu Yang, Chien-Wei Wu, Shuo-Wei Liang
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Publication number: 20090093093Abstract: A method for fabricating a thin film transistor (TFT) is provided. A substrate having a gate, a dielectric layer, a channel layer and an ohmic contact layer formed thereon is provided. Next, a metal layer is formed over the substrate covering the ohmic contact layer. Next, the metal layer and the ohmic contact layer are simultaneously etched by a wet etching process to form a source/drain and expose the channel layer. Because the wet etching process can be used to selectively etch the ohmic contact layer, damage to the underlying channel layer may be negligible. Thus, the reliability of the device may be promoted. Furthermore, the process may be simplified, the production yield and the throughput of TFT may be increased.Type: ApplicationFiled: December 11, 2007Publication date: April 9, 2009Applicants: TAIWAN TFT LCD ASSOCIATION, CHUNGHWA PICTURE TUBES, LTD., AU OPTRONICS CORPORATION, HANNSTAR DISPLAY CORPORATION, CHI MEI OPTOELECTRONICS CORPORATION, INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, TPO DISPLAYS CORP.Inventors: Sai-Chang Liu, Cheng-Tzu Yang, Chien-Wei Wu
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Publication number: 20080067148Abstract: An etchant for patterning composite layer containing copper is provided. The etchant includes peracetic acid being about 5% to 40% by weight and serving as a major component, a peracetic acid stabilizer being about 5% to 15% by weight, an organic acid being about 5% to 10% by weight, an inorganic acid being about 5% to 15% by weight, a salt being about 8% to 15% by weight, which are based on the total weight of the etchant.Type: ApplicationFiled: February 2, 2007Publication date: March 20, 2008Applicants: TAIWAN TFT LCD ASSOCIATION, CHUNGHWA PICTURE TUBES, LTD., AU OPTRONICS CORPORATION, HANNSTAR DISPLAY CORPORATION, CHI MEI OPTOELECTRONICS CORPORATION, INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, TPO DISPLAYS CORP.Inventors: Sai-Chang Liu, Cheng-Tzu Yang, Chien-Wei Wu, Shuo-Wei Liang
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Publication number: 20080057202Abstract: A method of fabricating of a metal line by a wet process is provided. A catalytic adhesive layer is formed on an insulating substrate. A fist metal layer is formed by an electoless plating process, and then, a second metal layer is formed by an electoless plating process or an electoplating process. The first and the second metal layers are patterned to form a metal line.Type: ApplicationFiled: November 21, 2006Publication date: March 6, 2008Applicants: TAIWAN TFT LCD ASSOCIATION, CHUNGHWA PICTURE TUBES, LTD., AU OPTRONICS CORPORATION, HANNSTAR DISPLAY CORPORATION, CHI MEI OPTOELECTRONICS CORPORATION, INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, TPO DISPLAYS CORP.Inventors: CHIEN-WEI WU, SHUO-WEI LIANG, WAN-CHI CHEN, CHENG-TZU YANG, SAI-CHANG LIU, PO-CHIU CHEN, MIN-CHUAN WANG, YUNG-CHIA KUAN