Patents by Inventor Cheng-Tzung Tsai
Cheng-Tzung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10573649Abstract: A semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate, a first fin formed on the first well, and a second fin formed on the second well. The first well includes a first conductivity type, the second well includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The substrate includes a first semiconductor material. The first fin and the second fin include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The first semiconductor material in the first fin includes a first concentration, the first semiconductor material in the second fin includes a second concentration, and the second concentration is larger than the first concentration.Type: GrantFiled: February 17, 2016Date of Patent: February 25, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chien-Hung Chen, Shih-Hsien Huang, Yu-Ru Yang, Chia-Hsun Tseng, Cheng-Tzung Tsai, Chun-Yuan Wu
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Patent number: 10439023Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.Type: GrantFiled: July 19, 2018Date of Patent: October 8, 2019Assignee: United Microelectronics Corp.Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee, Yu-Ru Yang, Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Cheng-Tzung Tsai
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Patent number: 10177231Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.Type: GrantFiled: October 30, 2017Date of Patent: January 8, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chien-Hung Chen, Shih-Hsien Huang, Yu-Ru Yang, Huai-Tzu Chiang, Hao-Ming Lee, Sheng-Hao Lin, Cheng-Tzung Tsai, Chun-Yuan Wu
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Publication number: 20180323256Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.Type: ApplicationFiled: July 19, 2018Publication date: November 8, 2018Applicant: United Microelectronics Corp.Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee, Yu-Ru Yang, Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Cheng-Tzung Tsai
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Patent number: 10068963Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.Type: GrantFiled: November 9, 2015Date of Patent: September 4, 2018Assignee: United Microelectronics Corp.Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee, Yu-Ru Yang, Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Cheng-Tzung Tsai
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Publication number: 20180053826Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.Type: ApplicationFiled: October 30, 2017Publication date: February 22, 2018Inventors: Chien-Hung Chen, Shih-Hsien Huang, Yu-Ru Yang, Huai-Tzu Chiang, Hao-Ming Lee, Sheng-Hao Lin, Cheng-Tzung Tsai, Chun-Yuan Wu
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Patent number: 9837493Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.Type: GrantFiled: November 13, 2015Date of Patent: December 5, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chien-Hung Chen, Shih-Hsien Huang, Yu-Ru Yang, Huai-Tzu Chiang, Hao-Ming Lee, Sheng-Hao Lin, Cheng-Tzung Tsai, Chun-Yuan Wu
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Publication number: 20170200721Abstract: A semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate, a first fin formed on the first well, and a second fin formed on the second well. The first well includes a first conductivity type, the second well includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The substrate includes a first semiconductor material. The first fin and the second fin include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The first semiconductor material in the first fin includes a first concentration, the first semiconductor material in the second fin includes a second concentration, and the second concentration is larger than the first concentration.Type: ApplicationFiled: February 17, 2016Publication date: July 13, 2017Inventors: Chien-Hung Chen, Shih-Hsien Huang, Yu-Ru Yang, Chia-Hsun Tseng, Cheng-Tzung Tsai, Chun-Yuan Wu
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Publication number: 20170104070Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.Type: ApplicationFiled: November 13, 2015Publication date: April 13, 2017Inventors: Chien-Hung Chen, Shih-Hsien Huang, Yu-Ru Yang, Huai-Tzu Chiang, Hao-Ming Lee, Sheng-Hao Lin, Cheng-Tzung Tsai, Chun-Yuan Wu
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Publication number: 20170098692Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.Type: ApplicationFiled: November 9, 2015Publication date: April 6, 2017Inventors: Huai-Tzu Chiang, Sheng-Hao Lin, Hao-Ming Lee, Yu-Ru Yang, Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Cheng-Tzung Tsai
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Patent number: 9590041Abstract: A semiconductor structure includes a semiconductor substrate, a dielectric structure formed on the semiconductor substrate and including at least a recess formed therein, a fin formed in the recess, and a dislocation region formed in the fin. The semiconductor substrate includes a first semiconductor material. The fin includes the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. A topmost portion of the dislocation region is higher than an opening of the recess.Type: GrantFiled: December 6, 2015Date of Patent: March 7, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ru Yang, Huai-Tzu Chiang, Sheng-Hao Lin, Shih-Hsien Huang, Chien-Hung Chen, Chun-Yuan Wu, Cheng-Tzung Tsai
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Patent number: 8592271Abstract: A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.Type: GrantFiled: May 16, 2013Date of Patent: November 26, 2013Assignee: United Microelectronics Corp.Inventors: Shih-Hung Tsai, Wen-Tai Chiang, Chen-Hua Tsai, Cheng-Tzung Tsai
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Publication number: 20130252387Abstract: A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.Type: ApplicationFiled: May 16, 2013Publication date: September 26, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shih-Hung Tsai, Wen-Tai Chiang, Chen-Hua Tsai, Cheng-Tzung Tsai
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Patent number: 8466502Abstract: A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.Type: GrantFiled: March 24, 2011Date of Patent: June 18, 2013Assignee: United Microelectronics Corp.Inventors: Shih-Hung Tsai, Wen-Tai Chiang, Chen-Hua Tsai, Cheng-Tzung Tsai
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Patent number: 8440514Abstract: A method for manufacturing a semiconductor device is provided. A gate structure is formed on a substrate. A first dopant implantation and a first strain atom implantation are performed. Thereafter, spacers are formed on sidewalls of the gate structure. A second dopant implantation and a second strain atom implantation are performed. A solid-phase epitaxy annealing process is performed to form source and drain regions made of a semiconductor compound solid-phase epitaxial layer beside the gate structure.Type: GrantFiled: April 11, 2008Date of Patent: May 14, 2013Assignee: United Microelectronics Corp.Inventors: Po-Wei Liu, Cheng-Tzung Tsai, Wen-Tai Chiang
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Publication number: 20120264297Abstract: In a method for creating a via in an IC manufacturing process, a substrate is provided and a circuitry structure is formed over the substrate. Then, a dielectric layer is formed over the circuitry structure; a hard mask is formed on and a trench is created through the dielectric layer; a coating layer is formed on the hard mask, filling the trench; an etch opening is defined in the coating layer by performing a pattern transfer process, wherein a width of the etch opening is greater than a width of the trench; and the bottom of the trench exposed from the etch opening is etched off with the hard mask, thereby creating a via for conductors.Type: ApplicationFiled: April 14, 2011Publication date: October 18, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chung-Fu CHANG, En-Chiuan Liou, I-Ming Tseng, Ssu-I Fu, Wen-Tai Chiang, Cheng-Tzung Tsai
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Publication number: 20120241868Abstract: A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.Type: ApplicationFiled: March 24, 2011Publication date: September 27, 2012Inventors: Shih-Hung Tsai, Wen-Tai Chiang, Chen-Hua Tsai, Cheng-Tzung Tsai
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Patent number: 8273642Abstract: A SiC region and a source/drain region are formed such that the SiC region includes a first portion overlapping the source/drain region and a second portion protruding from the source/drain region to a position beneath the LDD region. The concentration of crystalline SiC in the second portion is higher than the concentration of crystalline SiC in the first portion. The SiC region may be formed through a normal implantation before the second spacer is formed, or the SiC region may be formed through a tilt implantation or deposition epitaxially in a recess having a sigma-shape like sidewall after the second spacer is formed.Type: GrantFiled: October 4, 2010Date of Patent: September 25, 2012Assignee: United Microelectronics Corp.Inventors: Chen-Hua Tsai, Po-Jui Liao, Tzu-Feng Kuo, Ching-I Li, Cheng-Tzung Tsai
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Publication number: 20120199849Abstract: A method of fabrication of a metal oxide semiconductor field effect transistor includes first providing a substrate on which a gate structure is formed. Afterwards, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a number of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.Type: ApplicationFiled: April 13, 2012Publication date: August 9, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chen-Hua Tsai, Bang-Chiang Lan, Yu-Hsin Lin, Yi-Cheng Liu, Cheng-Tzung Tsai
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Patent number: 8207523Abstract: A method of fabrication of a metal oxide semiconductor field effect transistor is disclosed. At first, a substrate on which a gate structure is formed is provided. Afterward, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a plurality of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.Type: GrantFiled: April 26, 2006Date of Patent: June 26, 2012Assignee: United Microelectronics Corp.Inventors: Chen-Hua Tsai, Bang-Chiang Lan, Yu-Hsin Lin, Yi-Cheng Liu, Cheng-Tzung Tsai