Abstract: An apparatus for serial data communication between a plurality of IC chips with a reduced number of inter-chip signal lines. In the apparatus, one IC chip acts as a master, while the other chip(s) are slaved to it. In response to conditions internal to the master chip or in response to a request from at least one of the slave chips, the master chip generates a transfer control signal and a synchronization clock signal. The transfer control signal defines a transfer phase during which data transfer among the chips can take place. The chips take turns sending and receiving data in a multiplexed fashion, with sending and receiving parties designated by a count of synchronization clock signal cycles. The synchronization clock signal is generated at a high frequency, to allow fast data transfer.

Abstract: An apparatus for serial data communication between a plurality of IC chips with a reduced number of inter-chip signal lines. In the apparatus, one IC chip acts as a master, while the other chip(s) are slaved to it. In response to conditions internal to the master chip or in response to a request from at least one of the slave chips, the master chip generates a transfer control signal and a synchronization clock signal. The transfer control signal defines a transfer phase during which data transfer among the chips can take place. The chips take turns sending and receiving data in a multiplexed fashion, with sending and receiving parties designated by a count of synchronization clock signal cycles. The synchronization clock signal is generated at a high frequency, to allow fast data transfer.

Abstract: An apparatus for serial data communication between a plurality of IC chips with a reduced number of inter-chip signal lines. In the apparatus, one IC chip acts as a master, while the other chip(s) are slaved to it. In response to conditions internal to the master chip or in response to a request from at least one of the slave chips, the master chip generates a transfer control signal and a synchronization clock signal. The transfer control signal defines a transfer phase during which data transfer among the chips can take place. The chips take turns sending and receiving data in a multiplexed fashion. with sending and receiving parties designated by a count of synchronization clock signal cycles. The synchronization clock signal is generated at a high frequency, to allow fast data transfer.

Abstract: A self-adjusting apparatus including a clock generator built within an IC generates an adjusted internal oscillating clock signal by referring to an external target signal while the IC is running in a normal mode, and a method for adjusting the internal oscillating clock signal of an IC by using the apparatus. While an IC is operating in a normal mode, which is a more power-consuming mode, the apparatus adjusts the internal oscillating clock signal of the IC by referring to the frequency of an external clock signal generated by an external clock generator. When the IC is forced to run in a power-down mode, which consumes less power, the self-adjusting apparatus is still able to provide a precise internal oscillating clock signal required for operating the electronic circuit without the presence of an external clock signal.

Abstract: An apparatus for serial data communication between a plurality of IC chips with a reduced number of inter-chip signal lines. In the apparatus, one IC chip acts as a master, while the other chip(s) are slaved to it. In response to conditions internal to the master chip or in response to a request from at least one of the slave chips, the master chip generates a transfer control signal and a synchronization clock signal. The transfer control signal defines a transfer phase during which data transfer among the chips can take place. The chips take turns sending and receiving data in a multiplexed fashion, with sending and receiving parties designated by a count of synchronization clock signal cycles. The synchronization clock signal is generated at a high frequency, to allow fast data transfer.

Abstract: An apparatus that provides data communication between universal asynchronous receiver/transmitter (UART) modules on a first IC chip of a chip set and associated transceivers on a second IC chip of the same chip set. The apparatus includes a first multiplexer/demultiplexer unit coupled by first buses to the UART modules, and a second multiplexer/demultiplexer unit coupled by second buses to the transceivers. A common bus is interconnected between the first multiplexer/demultiplexer unit and the second multiplexer/demultiplexer unit. A control unit selectively connects the common bus to one of the first buses and one of the second buses so as to connect one of the UART modules in the first IC chip to the associated transceiver in the second IC chip.