Patents by Inventor Cheng-Wei Chiu

Cheng-Wei Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230345645
    Abstract: An electrical device includes a container, a conversion unit, an outer cover and an inner cover. The container is provided with an inner bottom surface and an inner which define an accommodating channel together. An inlet of the accommodating channel is opposite to the inner bottom surface. The conversion unit is disposed within the accommodating channel. The outer cover covers the inlet of the accommodating channel. The inner cover is disposed within the accommodating channel, and located between the conversion unit and the outer cover. One part of the conversion unit extends to the opening, and at least one outer edge of the inner cover is connected to an inner wall of the container.
    Type: Application
    Filed: October 20, 2022
    Publication date: October 26, 2023
    Inventors: Jen-Chieh TSAI, Chen-Wei LIU, Cheng-Wei CHIU, Yi-Chih HSU
  • Publication number: 20230339193
    Abstract: An ultrasonic welding device includes a first component and a second component. The first component includes at least one first welding feature and at least one second welding feature which are arranged along a horizontal direction, and the first and second welding features have different sizes in a vertical direction. The second component has at least one welding structure which is configured to be in contact with the first and second welding features, so as to weld the first and second components.
    Type: Application
    Filed: October 21, 2022
    Publication date: October 26, 2023
    Inventors: Jen-Chieh TSAI, Chen-Wei LIU, Cheng-Wei CHIU, Yi-Chih HSU
  • Patent number: 11723217
    Abstract: A magnetic memory element has a Ru hard mask layer. The use of Ru advantageously allows for closer spacing of adjacent magnetic memory elements leading to increased data density. In addition, the use of Ru as a hard mask reduces parasitic electrical resistance by virtue of the fact that Ru does not oxidize in ordinary manufacturing environments. The magnetic memory element can be formed by depositing a plurality of memory element layers, depositing a Ru hard mask layer, depositing a RIEable layer over the Ru hard mask layer, and forming a photoresist mask over the hard mask layer. A reactive ion etching can be performed to transfer the image of the photoresist mask onto the RIEable layer to form a RIEable mask. An ion etching can then be performed to transfer the image of the RIAable mask onto the underlying Ru hard mask and underlying memory element layers.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: August 8, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Mustafa Pinarbasi, Jacob Anthony Hernandez, Cheng Wei Chiu
  • Patent number: 11488961
    Abstract: A semiconductor device includes a substrate, an oxide layer and a word line. The substrate has a plurality of protruding portions. Adjacent two of the protruding portions define a dense zone, and another adjacent two of the protruding portions define a loose zone. The oxide layer is disposed on the substrate. The word line is disposed on the substrate. A bottom surface of a portion of the word line in the dense zone and a bottom surface of a portion of the word line in the loose zone are substantially at the same height.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: November 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Min-Chung Cheng, Chen-Tsung Liao, Cheng-Wei Chiu
  • Publication number: 20220285359
    Abstract: A semiconductor device includes a substrate, an oxide layer and a word line. The substrate has a plurality of protruding portions. Adjacent two of the protruding portions define a dense zone, and another adjacent two of the protruding portions define a loose zone. The oxide layer is disposed on the substrate. The word line is disposed on the substrate. A bottom surface of a portion of the word line in the dense zone and a bottom surface of a portion of the word line in the loose zone are substantially at the same height.
    Type: Application
    Filed: March 2, 2021
    Publication date: September 8, 2022
    Inventors: Min-Chung CHENG, Chen-Tsung LIAO, Cheng-Wei CHIU
  • Publication number: 20220238601
    Abstract: A magnetic memory element has a Ru hard mask layer. The use of Ru advantageously allows for closer spacing of adjacent magnetic memory elements leading to increased data density. In addition, the use of Ru as a hard mask reduces parasitic electrical resistance by virtue of the fact that Ru does not oxidize in ordinary manufacturing environments. The magnetic memory element can be formed by depositing a plurality of memory element layers, depositing a Ru hard mask layer, depositing a RIEable layer over the Ru hard mask layer, and forming a photoresist mask over the hard mask layer. A reactive ion etching can be performed to transfer the image of the photoresist mask onto the RIEable layer to form a RIEable mask. An ion etching can then be performed to transfer the image of the RIAable mask onto the underlying Ru hard mask and underlying memory element layers.
    Type: Application
    Filed: April 15, 2022
    Publication date: July 28, 2022
    Inventors: Mustafa Pinarbasi, Jacob Anthony Hernandez, Cheng Wei Chiu
  • Patent number: 11329100
    Abstract: A magnetic memory element having a Ru hard mask layer. The use of Ru advantageously allows for closer spacing of adjacent magnetic memory elements leading to increased data density. In addition, the use of Ru as a hard mask reduces parasitic electrical resistance by virtue of the fact that Ru does not oxidize in ordinary manufacturing environments. The magnetic memory element can be formed by depositing a plurality of memory element layers, depositing a Ru hard mask layer, depositing a RIEable layer over the Ru hard mask layer, and forming a photoresist mask over the hard mask layer. A reactive ion etching can be performed to transfer the image of the photoresist mask onto the RIEable layer to form a RIEable mask. An ion etching can then be performed to transfer the image of the RIAable mask onto the underlying Ru hard mask and underlying memory element layers.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: May 10, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Mustafa Pinarbasi, Jacob Anthony Hernandez, Cheng Wei Chiu
  • Patent number: 11283010
    Abstract: A magnetic memory element having a magnetic free layer and a magnetic reference layer with a non-magnetic barrier layer between the magnetic reference layer and the magnetic free layer. A spin current layer (which may be a precessional spin current layer) is located adjacent to the magnetic free layer and is separated from the magnetic free layer by a non-magnetic coupling layer. A material layer adjacent to and in contact with the spin current layer, has a material composition and thickness that are chosen to provide a desired effective magnetization in the spin current layer. The material layer, which may be a capping layer or a seed layer, can be constructed of a material other than tantalum which may include one or more of Zr, Mo, Ru, Rh, Pd, Hf, W, Ir, Pt and/or alloys and/or nitrides of these elements.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: March 22, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Jorge Vasquez, Bartlomiej Adam Kardasz, Cheng Wei Chiu, Mustafa Pinarbasi
  • Patent number: 10879454
    Abstract: A magnetic memory element for using in magnetic random access memory. The magnetic memory element includes a novel exchange coupling layer for use in an antiferromagnetic structure for magnetically pinning a magnetic reference layer of the memory element. The exchange coupling layer is located between a first magnetic layer (reference layer) and a second magnetic layer (keeper layer). The exchange coupling layer includes a layer of Ru located between first and second layers of Ir. The Ir layers can be in contact with each of the first and second magnetic layers to provide an interfacial magnetic anisotropy, as well as providing RKKY exchange field. The Ru layer, provides an increased RKKY exchange field as a result of the high RKKY exchange coupling of Ru.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: December 29, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Bartlomiej Adam Kardasz, Cheng Wei Chiu, Jorge Vasquez, Mustafa Pinarbasi
  • Publication number: 20200343298
    Abstract: A magnetic memory element having a Ru hard mask layer. The use of Ru advantageously allows for closer spacing of adjacent magnetic memory elements leading to increased data density. In addition, the use of Ru as a hard mask reduces parasitic electrical resistance by virtue of the fact that Ru does not oxidize in ordinary manufacturing environments. The magnetic memory element can be formed by depositing a plurality of memory element layers, depositing a Ru hard mask layer, depositing a RIEable layer over the Ru hard mask layer, and forming a photoresist mask over the hard mask layer. A reactive ion etching can be performed to transfer the image of the photoresist mask onto the RIEable layer to form a RIEable mask. An ion etching can then be performed to transfer the image of the RIAable mask onto the underlying Ru hard mask and underlying memory element layers.
    Type: Application
    Filed: April 23, 2019
    Publication date: October 29, 2020
    Inventors: Mustafa Pinarbasi, Jacob Anthony Hernandez, Cheng Wei Chiu
  • Publication number: 20150299514
    Abstract: A method for applying a coating to a surface of an industrial tool includes applying a coating including a thermosetting polymer to a metallic surface of the industrial tool. The coating is cured to form a bond between the coating and the metallic surface. According to certain embodiments, the thermosetting polymer may be combined with an additive. The additive may be selected to improve the chemical resistance or wear resistance of the coating and thereby improve the chemical resistance or wear resistance of certain surfaces of the industrial tool.
    Type: Application
    Filed: April 16, 2015
    Publication date: October 22, 2015
    Inventors: Cheng-Wei Chiu, David Michel Harrington
  • Publication number: 20150277622
    Abstract: A method for making a sensing circuit structure is disclosed to provide a transparent substrate, and then to form multiple plating base layers in the transparent substrate in a spaced manner, and then to form a metal conductor layer on each plating base layer using a plating technique. Thus, the thickness of the metal conductor layers can be thinner than that formed by silver paste. The invention relates also to a sensing circuit structure made by this method.
    Type: Application
    Filed: June 9, 2014
    Publication date: October 1, 2015
    Inventors: Po-Yi HSU, Cheng-Wei CHIU
  • Patent number: 7448129
    Abstract: A peel-off device for an electronic-part delivery system has a front end portion and a recess that is indented inwardly from the front end portion, that is formed through upper and lower surfaces of the front end portion and that has a width larger than that of an electronic part of predetermined specification.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: November 11, 2008
    Assignee: Asustek Computer, Inc.
    Inventors: Cheng-Wei Chiu, Kuo-Chou Cheng, Chin-Chan Chen, En-Hsien Lee, Wei-Sheng Hung
  • Publication number: 20050014293
    Abstract: A peel-off device for an electronic-part delivery system has a front end portion and a recess that is indented inwardly from the front end portion, that is formed through upper and lower surfaces of the front end portion and that has a width larger than that of an electronic part of predetermined specification.
    Type: Application
    Filed: June 24, 2004
    Publication date: January 20, 2005
    Applicant: ASUSTEK COMPUTER INC.
    Inventors: Cheng-Wei Chiu, Kuo-Chou Cheng, Chin-Chan Chen, En-Hsien Lee, Wei-Sheng Hung