Patents by Inventor Cheng-Wei Lin
Cheng-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240341061Abstract: A charging device includes a liquid cooled cable, a charging gun, a charging station, a station connector and a communicating pipe. The liquid cooled cable has a gun end and a station end. The liquid cooled cable includes a first insulating tube, a second insulating tube, a tape, a filler and a sheath. The first insulating tube has a first channel. The second insulating tube has a second channel and a braided copper mesh. The charging gun is connected to the gun end of the liquid cooled cable. The charging gun includes a gun connector and a first liquid return channel. The station connector includes a second liquid return channel and a connection part. One end of the second liquid return channel communicates to the second channel. The connection part is connected to the station end of the liquid cooled cable.Type: ApplicationFiled: May 9, 2023Publication date: October 10, 2024Inventors: Ko-Ming CHEN, Duan-Yih LIN, Cheng-Hong CHEN, Shih-Wei WANG, Shih-Hsiang WANG
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Patent number: 12107134Abstract: A device includes a semiconductor channel region and a gate structure. The semiconductor channel region is on a substrate. The gate structure is over the semiconductor channel region and comprises a gate dielectric layer, a first gate conductor layer, and a second gate conductor layer. The first gate conductor layer is over the gate dielectric layer. The first gate conductor layer includes oxygen. The second gate conductor layer is over the first gate conductor layer.Type: GrantFiled: December 13, 2022Date of Patent: October 1, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Ming Lin, Peng-Soon Lim, Zi-Wei Fang
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Publication number: 20240314976Abstract: A fluid immersion cooling system includes a fluid tank that contains a layer of a dual-phase coolant fluid and one or more layers of single-phase coolant fluids. The dual-phase and single-phase coolant fluids are immiscible, with the dual-phase coolant fluid having a lower boiling point and higher density than a single-phase coolant fluid. A substrate of an electronic system is submerged in the tank such that high heat-generating components are immersed at least in the layer of the dual-phase coolant fluid. Heat from the components is dissipated to the dual-phase coolant fluid to generate vapor bubbles of the dual-phase coolant fluid. The vapor bubbles rise to a layer of a single-phase coolant fluid that is above the layer of the dual-phase coolant fluid. The vapor bubbles condense to droplets of the dual-phase coolant fluid. The droplets fall down into the layer of the dual-phase coolant fluid.Type: ApplicationFiled: May 22, 2024Publication date: September 19, 2024Inventors: Yueh Ming LIU, Yu Hsiang HUANG, Yu Chuan CHANG, Tan Hsin CHANG, Hsiao Chung CHEN, Chia-Wei CHEN, Chih-Ta CHEN, Cheng-Hung LIN, Ming-Te HSU
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Publication number: 20240312901Abstract: An interconnect structure including a contact via in an interlayer dielectric, a first conductive feature in a first dielectric layer, the first dielectric layer over the interlayer dielectric, a first liner in the first dielectric layer, the first liner comprising a first part in contact with a sidewall surface of the first conductive feature, and a second part in contact with a bottom surface of the first conductive feature. The interconnect structure includes a first cap layer in contact with a top surface of the first conductive feature, a second conductive feature in a second dielectric layer, the second dielectric layer over the first dielectric layer, a second liner in the second dielectric layer, wherein the first and second conductive features comprise a first conductive material, and the contact via, first liner, first cap layer, and second liner comprise a second conductive material chemically different than the first conductive material.Type: ApplicationFiled: July 12, 2023Publication date: September 19, 2024Inventors: Chien CHANG, Yen-Chun LIN, Jen-Wei LIU, Chih-Han TSENG, Harry CHIEN, Cheng-Hui WENG, Chun-Chieh LIN, Hung-Wen SU, Ming-Hsing TSAI, Chih-Wei CHANG
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Publication number: 20240313091Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.Type: ApplicationFiled: May 22, 2024Publication date: September 19, 2024Inventors: Ryan Chia-Jen Chen, Li-Wei Yin, Tzu-Wen Pan, Cheng-Chung Chang, Shao-Hua Hsu, Yi-Chun Chen, Yu-Hsien Lin, Ming-Ching Chang
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Patent number: 12096657Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.Type: GrantFiled: October 18, 2021Date of Patent: September 17, 2024Assignee: Apple Inc.Inventors: Jung Yen Huang, Shinya Ono, Chin-Wei Lin, Akira Matsudaira, Cheng Min Hu, Chih Pang Chang, Ching-Sang Chuang, Gihoon Choo, Jiun-Jye Chang, Po-Chun Yeh, Shih Chang Chang, Yu-Wen Liu, Zino Lee
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Publication number: 20240300211Abstract: A laminated composite component is provided in this disclosure. The laminated composite component comprises a foam material layer, a first laminated sheet group and a second laminated sheet group. The foam material layer has a first surface and a second surface opposite to each other. The first laminated sheet group is disposed on the first surface. The second laminated sheet group is disposed on the second surface. The first laminated sheet group includes a plurality of first sheets. The second laminated sheet group includes a plurality of second sheets. The foam material layer, the first sheets of the first laminated sheet group, and the second sheets of the second laminated sheet group are laminated and pressed to form in one piece.Type: ApplicationFiled: February 20, 2024Publication date: September 12, 2024Applicant: Acer IncorporatedInventors: Dong-Sheng WU, Tzu-Wei LIN, Chih-Chun LIU, Cheng-Nan LING, Wen-Chieh TAI
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Patent number: 12086182Abstract: A method of building a knowledge graph, performed by a processing device, includes: classifying news articles to a main event associated with sub events, using the main event as a first node of the knowledge graph, using the sub events as second nodes of the knowledge graph respectively, connecting the second nodes to the first node, extracting event summaries from the news articles respectively according to a template, using the event summaries as third nodes of the knowledge graph respectively, and connecting each of the third nodes to one of the second nodes according to association between the event summaries and the sub events, extracting commenter identities from the event summaries, and using the commenter identities as fourth nodes of the knowledge graph, and connecting each of the fourth nodes to one of the third nodes.Type: GrantFiled: June 9, 2022Date of Patent: September 10, 2024Assignee: NATIONAL CHENG KUNG UNIVERSITYInventors: Wen-Hsiang Lu, Cheng-Wei Lin, Bo Yang Huang, Chia-Ming Tung
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Patent number: 12086241Abstract: The present invention provides an event visualization device configured to generate one or more directed acyclic graphs (DAGs) that can be used as a basis for diagnosing whether a target network system has been hacked according to a plurality of activities records. The plurality of activities records pertain to an event cluster associated with a suspicious event category. The event visualization device performs a graph generating operation on the plurality of activities records in a recursive manner to generate a hierarchical directed acyclic graph (HDAG). The graph generating operation includes: interpreting an activities record into a target DAG, and performing a hierarchical partial order alignment (HPOA) operation on the target DAG and a reference DAG to obtain a merging condition of each node; and merging the target DAG and the reference DAG into the HDAG according to the merging condition.Type: GrantFiled: July 18, 2022Date of Patent: September 10, 2024Assignee: CyCarrier Technology Co., Ltd.Inventors: Ming-Chang Chiu, Ming-Wei Wu, Pei-Kan Tsung, Che-Yu Lin, Cheng-Lin Yang
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Patent number: 12087575Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.Type: GrantFiled: January 18, 2022Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Hung-Yi Huang, Chun Chieh Wang, Yu-Ting Lin
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Publication number: 20240294321Abstract: A mask package comprises a package body, a cover body and a first buffer. The package body has a bottom and a side wall, where the side wall has a top; the side wall is connected with the bottom, the top is located on a side opposite to a side where the side wall is connected with the bottom, and the side wall surrounds the bottom to form an accommodating space. The cover body is disposed on the top of the side wall and masks the accommodating space. The first buffer has a first length and a first width, and is disposed between the package body and the cover body, where the accommodating space has a second length and a second width, the second length is less than the first length and the second width is less than the first width.Type: ApplicationFiled: July 26, 2023Publication date: September 5, 2024Inventor: Cheng-Wei Lin
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Patent number: 12081570Abstract: The present invention provides a log classification system configured to perform a hierarchical similarity analysis operation according to a plurality of activities records to generate a discrete space metric tree, and perform a clustering operation on the discrete space metric tree to generate one or more event clusters associated with one or more suspicious event categories. The log classification system includes an output device configured to output the one or more event clusters to an information security incident diagnosis system, and allow the information security incident diagnosis system to calculate similar feature information and differential feature information of a plurality of activities records in the one or more event clusters as auxiliary information for diagnosing whether there are intrusions or abnormalities in a target network system.Type: GrantFiled: July 18, 2022Date of Patent: September 3, 2024Assignee: CyCarrier Technology Co., Ltd.Inventors: Ming-Chang Chiu, Ming-Wei Wu, Pei-Kan Tsung, Che-Yu Lin, Cheng-Lin Yang
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Patent number: 12080594Abstract: An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.Type: GrantFiled: July 25, 2022Date of Patent: September 3, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Cheng-Lun Tsai, Huei-Wen Hsieh, Chun-Sheng Chen, Kai-Shiang Kuo, Jen-Wei Liu, Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su
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Publication number: 20240291524Abstract: Techniques pertaining to trigger-based (TB) implicit feedback for implicit beamforming in wireless communications are described. An apparatus (e.g., an access point (AP)) triggers each of one or more stations (STAs) to transmit a respective feedback. The apparatus estimates a respective steering matrix with respect to each of the one or more STAs based on the respective feedback. The apparatus then transmits a respective steered data to each of the one or more STAs based on the respective steering matrix.Type: ApplicationFiled: December 28, 2023Publication date: August 29, 2024Inventors: Cheng-En Hsieh, Ming-Hsiang Tseng, Kang-Li Wu, Shih-Wei Lin, Hao-Chih Yu, Ching-Yu Kuo, Hung-Tao Hsieh
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Patent number: 12074206Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.Type: GrantFiled: August 30, 2021Date of Patent: August 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Wei Chen, Chih-Yu Hsu, Hui-Chi Chen, Shan-Mei Liao, Jian-Hao Chen, Cheng-Hao Hou, Huang-Chin Chen, Cheng Hong Yang, Shih-Hao Lin, Tsung-Da Lin, Da-Yuan Lee, Kuo-Feng Yu, Feng-Cheng Yang, Chi On Chui, Yen-Ming Chen
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Patent number: 12068246Abstract: Exemplary embodiments for redistribution layers of integrated circuit components are disclosed. The redistribution layers of integrated circuit components of the present disclosure include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.Type: GrantFiled: November 27, 2018Date of Patent: August 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Yuan Li, Kuo-Cheng Lee, Yun-Wei Cheng, Yen-Liang Lin
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Patent number: 12062742Abstract: A package structure includes a substrate, a plurality of conductive pads, a light-emitting diode, a photo imageable dielectric material, and a black matrix. The substrate includes a top surface. The conductive pads are located on the top surface of the substrate. The light-emitting diode is located on the conductive pads. The photo imageable dielectric material is located between the light-emitting diode and the top surface of the substrate and between the conductive pads. An orthogonal projection of the light-emitting diode on the substrate is overlapped with an orthogonal projection of the photo imageable dielectric material on the substrate. The black matrix is located on the top surface of the substrate and the conductive pads.Type: GrantFiled: March 7, 2022Date of Patent: August 13, 2024Assignee: Unimicron Technology Corp.Inventors: Hao-Wei Tseng, Chi-Hai Kuo, Jeng-Ting Li, Ying-Chu Chen, Pu-Ju Lin, Cheng-Ta Ko
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Patent number: 12057079Abstract: A display device is disclosed. The display device includes a display panel, a backlight module, and a processor. The display panel displays a display screen. The backlight module provides a backlight brightness to the display panel. The processor generates the display screen and determines the backlight brightness corresponding to the display screen. The processor dynamically adjusts a size and a position of several display areas on the display screen based on an instant state of the continuous image signal respectively. The processor determines several backlight areas corresponding to several display areas respectively, and the processor generates several backlight control signals corresponding to several backlight areas respectively based on the display setting and several image contents.Type: GrantFiled: January 19, 2023Date of Patent: August 6, 2024Assignee: AmTRAN Technology Co., Ltd.Inventors: Cheng-En Hsiao, Chia-Wei Lin, Che-Chia Ho
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Patent number: 12051944Abstract: A rotor includes a stack of electromagnetic steel plates each including through-hole groups with through-holes extending through the respective electromagnetic steel plates. In each of the through-hole groups, at least one of the through-holes accommodates a magnet and at least a portion of the through-holes that does not accommodate any magnet is filled with an electrically conductive material. When the rotor is seen axially, at two circumferential sides of a magnetic flux passage that is adjacent to the magnet, a width of the magnetic flux passage adjacent a first side of the magnet is larger than a width of the magnetic flux passage near a second side of the magnet.Type: GrantFiled: August 27, 2020Date of Patent: July 30, 2024Assignee: NIDEC CORPORATIONInventors: Yu-Wei Hsu, Ta-Yin Luo, Hsin-Nan Lin, Sheng-Chan Yen, Guo-Jhih Yan, Cheng-Tsung Liu
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Publication number: 20240249948Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.Type: ApplicationFiled: March 28, 2024Publication date: July 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Wei CHANG, Kao-Feng LIN, Min-Hsiu HUNG, Yi-Hsiang CHAO, Huang-Yi HUANG, Yu-Ting LIN