Patents by Inventor Cheng-Wen Chiu
Cheng-Wen Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162833Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.Type: ApplicationFiled: November 13, 2023Publication date: May 16, 2024Inventors: Yi-Sheng CHANG, Cheng-Chan HSU, Chia-Wei CHU, Chun-Yu YANG, Deng-Cyun HUANG, Yi-Hsun CHIU, Chien-An LAI, Yu-Tai WANG, Chi-Shou HO, Zhi-Yuan WU, Ko-Wen LU
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Publication number: 20240145581Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Wen CHIU, Yi Che CHAN, Lun-Kuang TAN, Zheng-Yang PAN, Cheng-Po CHAU, Pin-Chu LIANG, Hung-Yao CHEN, De-Wei YU, Yi-Cheng LI
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Patent number: 11942420Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.Type: GrantFiled: June 8, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Guo-Huei Wu, Hui-Zhong Zhuang, Chih-Liang Chen, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu
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Publication number: 20240096805Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Inventors: Shang-Wen Chang, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Wei-Cheng Lin, Shih-Wei Peng, Jiann-Tyng Tzeng
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Patent number: 11935957Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.Type: GrantFiled: August 9, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
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Patent number: 9455159Abstract: A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer.Type: GrantFiled: September 25, 2015Date of Patent: September 27, 2016Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wei-Ping Wang, Pang-Chun Lin, Chin-Chih Hsiao, Kuan-I Cheng, Cheng-Wen Chiu
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Publication number: 20160013074Abstract: A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer.Type: ApplicationFiled: September 25, 2015Publication date: January 14, 2016Inventors: Wei-Ping Wang, Pang-Chun Lin, Chin-Chih Hsiao, Kuan-I Cheng, Cheng-Wen Chiu
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Patent number: 9171741Abstract: A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer.Type: GrantFiled: August 3, 2012Date of Patent: October 27, 2015Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wei-Ping Wang, Pang-Chun Lin, Chin-Chih Hsiao, Kaun-i Cheng, Cheng-Wen Chiu
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Publication number: 20130115738Abstract: A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer.Type: ApplicationFiled: August 3, 2012Publication date: May 9, 2013Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Wei-Ping Wang, Pang-Chun Lin, Chin-Chih Hsiao, Kaun-i Cheng, Cheng-Wen Chiu