Patents by Inventor Cheng Xiao

Cheng Xiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12299371
    Abstract: A device including functional blocks and dummy cells. The functional blocks include a first functional block and a second functional block. Each dummy cell having a cell boundary defined by non-functioning active areas and non-functioning gates for filling space between the functional blocks and including a dummy cell configured to be situated between the first functional block and the second functional block such that the dummy cell directly abuts each of the first functional block and the second functional block.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yeh Yu, Wei-Yi Hu, Shih-Hsuan Chien, You-Cheng Xiao, Ya-Chi Chou
  • Publication number: 20250021736
    Abstract: A device including functional blocks and dummy cells. The functional blocks include a first functional block and a second functional block. Each dummy cell having a cell boundary defined by non-functioning active areas and non-functioning gates for filling space between the functional blocks and including a dummy cell configured to be situated between the first functional block and the second functional block such that the dummy cell directly abuts each of the first functional block and the second functional block.
    Type: Application
    Filed: July 26, 2024
    Publication date: January 16, 2025
    Inventors: Chi-Yeh Yu, Wei-Yi Hu, Shih-Hsuan Chien, You-Cheng Xiao, Ya-Chi Chou
  • Patent number: 12167583
    Abstract: A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Cheng Xiao, Jhih-Siang Hu, Ru-Yu Wang, Jung-Hsuan Chen, Ting-Wei Chiang
  • Publication number: 20240397698
    Abstract: A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Cheng XIAO, Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan CHEN, Ting-Wei CHIANG
  • Publication number: 20240397697
    Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell. The at least one logic cell includes fins. The fins are separated into fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Cheng XIAO, Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan CHEN, Ting-Wei CHIANG
  • Publication number: 20240395794
    Abstract: A semiconductor device includes a substrate; and a cell region having opposite first and second sides, the cell region including active regions formed in the substrate; relative to an imaginary first reference line, a first majority of the active regions having first ends which align with the first reference line, the first side being parallel and proximal to the first reference line; relative to an imaginary second reference line in the second direction, a second majority of the active regions having second ends which align with the second reference line, the second side being parallel and proximal to the second reference line; and gate structures correspondingly on first and second ones of the active regions; and relative to the second direction, a first end of a selected one of the gate structures abuts an intervening region between the first and second active regions.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Ru-Yu WANG, You-Cheng XIAO, Kao-Cheng LIN, Pin-Dai SUE, Ting-Wei CHIANG
  • Publication number: 20240357792
    Abstract: A semiconductor arrangement includes a memory array including bitcells and a peripheral logic block for accessing the bitcells. The peripheral logic block includes a first nanostructure having a first width for providing power to a first logic unit of the peripheral logic block, and a second nanostructure axially aligned with the first nanostructure and having a second width less than the first width for providing power to a second logic unit of the peripheral logic block.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventors: Po-Sheng WANG, Ru-Yu WANG, Yangsyu LIN, You-Cheng XIAO
  • Patent number: 12048137
    Abstract: A semiconductor arrangement includes a memory array including bitcells and a peripheral logic block for accessing the bitcells. The peripheral logic block includes a first nanostructure having a first width for providing power to a first logic unit of the peripheral logic block, and a second nanostructure axially aligned with the first nanostructure and having a second width less than the first width for providing power to a second logic unit of the peripheral logic block.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Po-Sheng Wang, Ru-Yu Wang, Yangsyu Lin, You-Cheng Xiao
  • Publication number: 20240199654
    Abstract: A CTLA-4 small molecule degradation agent and an application thereof. The CTLA-4 small molecule degradation agent comprises a compound having the structure represented by formula I or a pharmaceutically acceptable salt, an ester, a deuterated product, an isomer, a solvate, a prodrug, or an isotopic label thereof: a new class of small molecule compounds having high degradation activity on CTLA-4. The compounds show a good degradation activity on CTLA-4 at the nanomolar (nM) level in in vitro studies.
    Type: Application
    Filed: March 17, 2022
    Publication date: June 20, 2024
    Applicant: SUZHOU GUOKUANG PHARMTECH. CO., LTD.
    Inventors: Desheng MEI, Baokun HE, Shiming LV, Gaorui SUN, Kui WANG, Cheng XIAO, Min LIANG, Xin LING, Shuaishuai LIU
  • Publication number: 20230289508
    Abstract: A device including functional blocks and dummy cells. The functional blocks include a first functional block and a second functional block. Each dummy cell having a cell boundary defined by non-functioning active areas and non-functioning gates for filling space between the functional blocks and including a dummy cell configured to be situated between the first functional block and the second functional block such that the dummy cell directly abuts each of the first functional block and the second functional block.
    Type: Application
    Filed: June 29, 2022
    Publication date: September 14, 2023
    Inventors: Chi-Yeh Yu, Wei-Yi Hu, Shih-Hsuan Chien, You-Cheng Xiao, Ya-Chi Chou
  • Publication number: 20230124337
    Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell. The at least one logic cell includes fins. The fins are separated into fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 20, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Cheng XIAO, Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan CHEN, Ting-Wei CHIANG
  • Publication number: 20230111939
    Abstract: A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 13, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Cheng XIAO, Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan CHEN, Ting-Wei CHIANG
  • Publication number: 20230042514
    Abstract: A semiconductor device includes a substrate; and a cell region having opposite first and second sides, the cell region including active regions formed in the substrate; relative to an imaginary first reference line, a first majority of the active regions having first ends which align with the first reference line, the first side being parallel and proximal to the first reference line; relative to an imaginary second reference line in the second direction, a second majority of the active regions having second ends which align with the second reference line, the second side being parallel and proximal to the second reference line; and gate structures correspondingly on first and second ones of the active regions; and relative to the second direction, a first end of a selected one of the gate structures abuts an intervening region between the first and second active regions.
    Type: Application
    Filed: January 21, 2022
    Publication date: February 9, 2023
    Inventors: Ru-Yu WANG, You-Cheng XIAO, Kao-Cheng LIN, Pin-Dai SUE, Ting-Wei CHIANG
  • Patent number: 11552085
    Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell and includes a plurality of fins. The plurality of fins are separated into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method is also disclosed herein.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Cheng Xiao, Jhih-Siang Hu, Ru-Yu Wang, Jung-Hsuan Chen, Ting-Wei Chiang
  • Publication number: 20220302136
    Abstract: A semiconductor arrangement includes a memory array including bitcells and a peripheral logic block for accessing the bitcells. The peripheral logic block includes a first nanostructure having a first width for providing power to a first logic unit of the peripheral logic block, and a second nanostructure axially aligned with the first nanostructure and having a second width less than the first width for providing power to a second logic unit of the peripheral logic block.
    Type: Application
    Filed: August 17, 2021
    Publication date: September 22, 2022
    Inventors: Po-Sheng WANG, Ru-Yu WANG, Yangsyu LIN, You-Cheng XIAO
  • Publication number: 20220102363
    Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell and includes a plurality of fins. The plurality of fins are separated into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method is also disclosed herein.
    Type: Application
    Filed: September 28, 2020
    Publication date: March 31, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Cheng XIAO, Jhih-Siang HU, Ru-Yu WANG, Jung-Hsuan CHEN, Ting-Wei CHIANG
  • Patent number: 10141797
    Abstract: An electric motor has a polygon stator core. The polygon stator core includes yoke portions and teeth extending inwardly from the yoke portions. A winding slot is formed between adjacent teeth. Adjacent yoke portions are interconnected by a connecting portion. The winding slots include first winding slots and second winding slots of different shapes. The ratio of the area of a first winding slot to the area of a second winding slot is greater than or equal to 0.9 but less than or equal to 1.1. By changing the shape of the stator core, the size of the winding slots may be increased without increasing the radial dimension of the motor.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: November 27, 2018
    Assignee: JOHNSON ELECTRIC S.A.
    Inventors: Rui Feng Qin, Fei Liu, Hong Liang Zhang, Jiang Cheng Xiao, Hai Qiang Zhou
  • Publication number: 20170231922
    Abstract: Disclosed herein are methods for treating skin conditions associated with skin parasites, including mites, by administering a therapeutically effective amount of 3,5-dihydroxy-4-isopropyl-trans-stilbene (DHIS).
    Type: Application
    Filed: February 16, 2016
    Publication date: August 17, 2017
    Inventors: Youwen Zhou, Cheng Xiao, Yang Wang, Yuanshen Huang, Mingwan Su
  • Patent number: 9530727
    Abstract: A method comprises: forming a plurality of reference voltage patterns in a first layer of a semiconductor substrate using a first mask, the reference voltage patterns including alternating first reference voltage patterns and second reference voltage patterns; and forming a plurality of signal patterns in the first layer of the semiconductor substrate using a second mask, ones of the plurality of signal patterns located between successive pairs of reference voltage patterns.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: You-Cheng Xiao, Wei Min Chan, Ken-Hsien Hsieh
  • Patent number: 9425095
    Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.
    Type: Grant
    Filed: May 24, 2015
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Cheng Xiao, Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Li-Chun Tien, Hung-Jen Liao