Patents by Inventor Cheng-Ya LEE

Cheng-Ya LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250118598
    Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a first dielectric layer, a first conductive feature, a second dielectric layer, and a barrier layer. The first conductive feature is disposed on the first dielectric layer, the second dielectric layer is disposed on the first dielectric layer and surrounds the sidewalls of the first conductive feature, the barrier layer is disposed between the first dielectric layer and the second dielectric layer and between the sidewalls of the first conductive feature and the second dielectric layer.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Shao-Kuan LEE, Kuang-Wei YANG, Gary HSU WEI LIU, Yen-Ju WU, Jing-Ting SU, Hsin-Yen HUANG, Hsiao-Kang CHANG, Wei-Chen CHU, Shu-Yun KU, Chia-Tien WU, Ming-Han LEE, Hsin-Ping CHEN
  • Patent number: 12230537
    Abstract: A method for forming an interconnect structure includes forming a first conductive layer over a dielectric layer, forming one or more openings in the first conductive layer to expose portions of dielectric surface of the dielectric layer and conductive surfaces of the first conductive layer, wherein the one or more openings separates the first conductive layer into one or more portions.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Ya Lo, Cheng-Chin Lee, Shao-Kuan Lee, Chi-Lin Teng, Hsin-Yen Huang, Hsiaokang Chang, Shau-Lin Shue
  • Publication number: 20250046673
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.
    Type: Application
    Filed: October 22, 2024
    Publication date: February 6, 2025
    Inventors: Shao-Kuan Lee, Cherng-Shiaw Tsai, Ting-Ya Lo, Cheng-Chin Lee, Chi-Lin Teng, Kai-Fang Cheng, Hsin-Yen Huang, Hsiao-Kang Chang, Shau-Lin Shue
  • Publication number: 20210196208
    Abstract: A physiological signal sensing and compensation system is provided, for contacting an object to be measured and sensing a physiological signal. The physiological signal sensing and compensation system includes a physiological signal sensing module, a compensation module, and a computing unit. The physiological signal sensing module provides an initial sensing signal. The compensation module includes a collecting mechanism for collecting a physiological liquid of the object to be measured. The compensation module provides a compensation signal according to the physiological liquid collected by the collection mechanism. The computing unit is electrically connected to the physiological signal sensing module and the compensation module, and calculates and provides a compensated sensing signal based on the initial sensing signal and the compensation signal.
    Type: Application
    Filed: April 17, 2020
    Publication date: July 1, 2021
    Inventors: Shuen-Yu YU, Cheng-Ya LEE, Kuang-Ching FAN