Patents by Inventor CHENG-YAN WEN

CHENG-YAN WEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit test method
    Patent number: 10496505
    Abstract: The present invention discloses an IC test method including the following steps: generating N test patterns; testing each of M chip(s) according to the N test patterns so as to generate N×M records of quiescent DC current (IDDQ) data; generating N reference values according to the N×M records, in which each of the N reference values is generated according to M record(s) of the N×M records, and the M record(s) and the reference value generated thereupon are related to the same one of the N test patterns; obtaining a reference order of the N test patterns according to the N reference values and a sorting rule; reordering the N×M records by the reference order so as to obtain reordered N×M records; generating an IDDQ range according to the reordered N×M records; and determining whether any of the M chip(s) is defective based on the IDDQ range.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: December 3, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Wen-Hsuan Hsu, Ying-Yen Chen, Cheng-Yan Wen, Chia-Tso Chao, Jih-Nung Lee
  • INTEGRATED CIRCUIT TEST METHOD
    Publication number: 20180181477
    Abstract: The present invention discloses an IC test method including the following steps: generating N test patterns; testing each of M chip(s) according to the N test patterns so as to generate N×M records of quiescent DC current (IDDQ) data; generating N reference values according to the N×M records, in which each of the N reference values is generated according to M record(s) of the N×M records, and the M record(s) and the reference value generated thereupon are related to the same one of the N test patterns; obtaining a reference order of the N test patterns according to the N reference values and a sorting rule; reordering the N×M records by the reference order so as to obtain reordered N×M records; generating an IDDQ range according to the reordered N×M records; and determining whether any of the M chip(s) is defective based on the IDDQ range.
    Type: Application
    Filed: December 6, 2017
    Publication date: June 28, 2018
    Inventors: WEN-HSUAN HSU, YING-YEN CHEN, CHENG-YAN WEN, CHIA-TSO CHAO, JIH-NUNG LEE