Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.

Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.

Abstract: The disclosure provides a structure diagnosis system and a structure diagnosis method. The structure diagnosis system includes: a lidar scanner scanning a structure to generate a point cloud data; an input interface receiving the point cloud data; and a processor receiving the point cloud data and generating a point cloud data set. The processor executes a surface degradation and geometry abnormal coupling diagnosis module to: marking a first point cloud range of a surface degradation area according to color space value of the point cloud data set; marking a second point cloud range of a geometry abnormal area according to coordinate value of the point cloud data set; when an abnormal area includes the first point cloud range and the second point cloud range at least partially overlapping each other, determining surface degradation or geometry abnormal occurring at the abnormal area and mark the abnormal area with a predetermined mode.

Abstract: An electronic device includes an electronic module, a protective substrate on the electronic module, and a functional layer on the protective substrate. The functional layer has a hardness in a range of 4H to 9H. A manufacturing method of the electronic device comprises providing a protective substrate having a first surface and a second surface opposite to the first surface; forming a preparatory layer on the first surface; performing a heat treatment to convert the preparatory layer to a functional layer; and disposing an electronic module on the second surface, wherein the heat treatment is performed in a range of 200° C. to 1200° C.

Abstract: The disclosure provides a structure diagnosis system and a structure diagnosis method. The structure diagnosis system includes: a lidar scanner scanning a structure to generate a point cloud data; an input interface receiving the point cloud data; and a processor receiving the point cloud data and generating a point cloud data set. The processor executes a surface degradation and geometry abnormal coupling diagnosis module to: marking a first point cloud range of a surface degradation area according to color space value of the point cloud data set; marking a second point cloud range of a geometry abnormal area according to coordinate value of the point cloud data set; when an abnormal area includes the first point cloud range and the second point cloud range at least partially overlapping each other, determining surface degradation or geometry abnormal occurring at the abnormal area and mark the abnormal area with a predetermined mode.

Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.

Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.

Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.

Abstract: A speed-up charge pump includes a first charge pump for receiving an up signal and a down signal in digital form to produce a first voltage control signal at an output node. Further, at least one speed-up phase detector includes a first circuit path to receive the up signal and delay the up signal by a predetermined delay as a delay up signal and operate the up signal and the delay up signal by AND logic into an auxiliary up signal; and a second circuit path to receive the down signal and delay the down signal by the predetermined delay as a delay down signal and operate the down signal and the delay down signal by AND logic into an auxiliary down signal. A second charge pump is respectively receiving the auxiliary up and down signals to produce a second voltage control signal also at the output node.

Abstract: A method for manufacturing a water-based coating material is provided, including: (a) reacting tetraalkoxysilane, acidic aqueous solution of vanadium salt, and trialkoxyalkylsilane to form an oligomer; (b) reacting the oligomer with colloidal silica particles to form a modified oligomer; and (c) reacting the modified oligomer with trialkoxyepoxysilane to obtain a water-based coating material.

Abstract: An adaptability job vacancies matching system and method are provided. The system performs the following operations: determining a target corpus based on the electronic resume; analyzing the electronic resume to generate a plurality of keyword sets; analyzing the keyword sets to generate an electronic resume score; generating a plurality of interview questions according to the keyword sets and a plurality of preset question sets corresponding to a target job category; transmitting an animation to a user device, the animation is related to the interview questions; receiving a response animation, the response animation is related to a response of each interview question; analyzing the response animation, and generating an interview question score of each interview question and a confidence score corresponding to each interview question; calculating an index score based on the electronic resume score, the interview question scores, and the confidence scores to generate a list of matching job vacancies.

Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.

Abstract: The present invention provides an integrated circuit with a standard cell of an inverter standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

Abstract: The present invention provides an integrated circuit with a standard cell of an inverter. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

Abstract: The present invention provides an integrated circuit with a standard cell of an inverter. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

Abstract: The present invention provides an integrated circuit with a standard cell of an inverter standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Two long contact plugs disposed at one side of the gate structure; two short contact plugs disposed at the other side of the gate structure; a gate contact plug disposed on the gate structure; Plural via plugs disposed on the long contact plugs, the short contact plugs and the gate contact plugs; A metal layer includes the first metal line, the second metal line, a third metal line and a fourth metal line.

Abstract: The present invention provides an integrated circuit with a dummy standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Plural sets of short contact plug and long contact plug disposed between the first dummy gate, the second dummy gate and the gate structures; a doping region overlaps with the long contact plugs; a gate contact plug disposed on the gate structures; plural contact plugs disposed on and electrical contact the long contact plugs; A metal layer includes the first metal line, the second metal line.

Abstract: A voltage detection circuit comprises a plurality of even-number voltage detection nodes, at least one odd-number voltage detection node, a voltage differential generation circuit, a selection circuit and a computing circuit. The selection circuit is for controlling the coupling relationship between the voltage differential generation circuit and the even and odd-number voltage detection nodes, so that the voltage differential generation circuit generates a voltage differential between the nodes. The computing circuit knows a voltage of a first even-number voltage detection node being as a reference voltage or obtains the voltage of the first even-number voltage detection node on the basis of the reference voltage, and respectively obtains a voltage of the nodes on the basis of the voltage differential between two adjacent nodes and the obtained voltage of a first even-number voltage detection node.

Abstract: A voltage detection circuit comprises a plurality of even-number voltage detection nodes, at least one odd-number voltage detection node, a voltage differential generation circuit, a selection circuit and a computing circuit. The selection circuit is for controlling the coupling relationship between the voltage differential generation circuit and the even and odd-number voltage detection nodes, so that the voltage differential generation circuit generates a voltage differential between the nodes. The computing circuit knows a voltage of a first even-number voltage detection node being as a reference voltage or obtains the voltage of the first even-number voltage detection node on the basis of the reference voltage, and respectively obtains a voltage of the nodes on the basis of the voltage differential between two adjacent nodes and the obtained voltage of a first even-number voltage detection node.

Abstract: The shoe has a body, an insole, illuminating device and a shoe-pad. The body is formed as a single piece and has a recess, a heel, and a cavity. The cavity is formed in the body near the heel and communicates with the recess. The insole is mounted in the recess and has a crevice, a containing hole and a fixing hole. The crevice is formed in the bottom of the insole and corresponds to the cavity in the body. The containing hole is formed in the insole and corresponds to the cavity, and the fixing hole is formed in the periphery of the insole. The illuminating device is mounted between the body and the insole and has two wires, a power source, a circuit board, multiple illuminating elements and a switch. The shoe-pad is attached to insole and has a through hole and a cover.