Patents by Inventor Cheng-Yao Lo
Cheng-Yao Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105865Abstract: An optoelectronic device includes a first electrode, a second electrode that is spaced apart from the first electrode, an optoelectronic unit that is disposed between the first electrode and the second electrode, an insulating layer and a driving electrode. The optoelectronic unit includes an optoelectronic stack emitting or absorbing at least two wavelengths of light. The insulating layer is disposed on a lateral side of the optoelectronic stack that extends in a stacking direction of the optoelectronic stack. The driving electrode is disposed on the insulating layer at a location corresponding in position to the optoelectronic unit and is separated from the first and second electrodes.Type: ApplicationFiled: April 18, 2023Publication date: March 28, 2024Applicant: National Tsing Hua UniversityInventors: Cheng-Yao LO, Padmanabh Pundrikaksha PANCHAM, Yu-Xin ZENG, Chih-Liang PAN
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Publication number: 20170031184Abstract: The present invention provides a pixel for realizing a full-color display, including an elastomer; and a plurality of microstructures disposed on the elastomer, wherein the pixel is composed of a single sub-pixel and the plurality of microstructures have the same primary morphology; wherein when applying a force to the elastomer, the plurality of microstructures have a second morphology which is different from the primary morphology. The present invention also provides a micro-electro-mechanical system (MEMS) for realizing a full-color display, fabrication methods thereof, and a method to realize a full-color display with a single pixel.Type: ApplicationFiled: April 8, 2016Publication date: February 2, 2017Inventors: Cheng-Yao LO, Chien-Wei HUNG, Yi-Chu CHEN
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Publication number: 20150043610Abstract: A system and a method for stress detection on small areas are disclosed. The method is applied to a strain gauge, which uses the Joule heating effect-generated temperature difference to monitor and to localize compressive and tensile strains. Furthermore, the invention provides a systematic extrapolation prediction methodology for strains.Type: ApplicationFiled: November 20, 2013Publication date: February 12, 2015Applicant: NATIONAL TSING HUA UNIVERSITYInventors: Cheng-Yao LO, Kuan-Hsun LIAO
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Patent number: 8837035Abstract: An electro-wetting transmissive and interference display device with adjustable function includes a lower electrode, an upper electrode and an droplet disposed between the upper electrode and the lower electrode, wherein the lower electrode, the droplet and the upper electrode are disposed on a substrate, and the droplet is enclosed between the lower electrode and the upper electrode by an ink jet printing method.Type: GrantFiled: January 3, 2013Date of Patent: September 16, 2014Assignee: National Tsing Hua UniversityInventors: Jux Win, Wei-Leun Fang, Cheng-Yao Lo
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Publication number: 20140043670Abstract: An electro-wetting transmissive and interference display device with adjustable function includes a lower electrode, an upper electrode and an droplet disposed between the upper electrode and the lower electrode, wherein the lower electrode, the droplet and the upper electrode are disposed on a substrate, and the droplet is enclosed between the lower electrode and the upper electrode by an ink jet printing method.Type: ApplicationFiled: January 3, 2013Publication date: February 13, 2014Applicant: National Tsing Hua UniversityInventors: Jux WIN, Wei-Leun FANG, Cheng-Yao LO
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Publication number: 20130213817Abstract: A method for shrinking a linewidth on a substrate includes the steps of applying a stretching force on the substrate, defining a line on a top surface of the substrate and releasing the applied stretching force. The applied force is executed by mechanical stretching or thermal expansion and has a direction parallel to the line.Type: ApplicationFiled: May 11, 2012Publication date: August 22, 2013Inventors: Cheng-Yao LO, Kuan-Hsun Liao
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Publication number: 20130033710Abstract: A non-energy dissipating, curvature sensing device senses curvature variation of a sample and comprises an outer layer, an inner layer and at least one spacer. The outer layer is flexible, transparent material and has a shape. The inner layer is flexible, transparent material, has a shape corresponding to the shape of the outer layer, is positioned under the outer layer and is thicker and harder than the outer layer. At least one spacer is positioned between the outer layer and the inner layer and creates space between the outer layer and the inner layer. A non-energy dissipating, curvature sensing method is also disclosed.Type: ApplicationFiled: October 14, 2011Publication date: February 7, 2013Applicant: National Tsing Hua UniversityInventors: Cheng-Yao LO, Sheng-An KUO
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Publication number: 20120293491Abstract: A 3-D touch panel includes a 3-D touch sensor, a capacitance sensing unit electrically connected to the 3-D touch sensor, and a processing unit electrically connected to capacitance sensing unit. The 3-D touch sensor includes a flexible substrate, a flexible plane, a first electrode, and a second electrode. The flexible plane is configured on the flexible substrate and used for a user to touch thereon. The first electrode and the second electrode are correspondingly and respectively configured on the flexible substrate and the flexible plane, and a capacitance is formed between the first electrode and the second electrode. The capacitance sensing unit is used for sensing the value of the capacitance, and the processing unit calculates the shearing force, which the user applies on the flexible plane, according to the difference of the capacitance value.Type: ApplicationFiled: July 12, 2011Publication date: November 22, 2012Applicant: NATIONAL TSING HUA UNIVERSITYInventors: YUNG-CHEN WANG, TSUN-YI CHEN, RONG-SHUN CHEN, CHENG-YAO LO
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Patent number: 7772051Abstract: A MOS device having corner spacers and a method for forming the same are provided. The method includes forming a gate structure overlying a substrate, forming a first dielectric layer over the gate structure and the substrate, forming a second dielectric layer on the first dielectric layer, forming a third dielectric layer on the second dielectric layer, and etching the first, the second and the third dielectric layers using the third dielectric layer as a mask. The remaining first and second dielectric layers have an L-shape. The method further includes implanting source/drain regions, removing remaining portions of the third dielectric layer, blanket forming a fourth dielectric layer, etching the fourth dielectric layer, siliciding exposed source/drain regions, and forming a contact etch stop layer. The remaining portion of the fourth dielectric layer forms corner spacers.Type: GrantFiled: January 15, 2009Date of Patent: August 10, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Cheng-Yao Lo
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Publication number: 20090176344Abstract: A MOS device having corner spacers and a method for forming the same are provided. The method includes forming a gate structure overlying a substrate, forming a first dielectric layer over the gate structure and the substrate, forming a second dielectric layer on the first dielectric layer, forming a third dielectric layer on the second dielectric layer, and etching the first, the second and the third dielectric layers using the third dielectric layer as a mask. The remaining first and second dielectric layers have an L-shape. The method further includes implanting source/drain regions, removing remaining portions of the third dielectric layer, blanket forming a fourth dielectric layer, etching the fourth dielectric layer, siliciding exposed source/drain regions, and forming a contact etch stop layer. The remaining portion of the fourth dielectric layer forms corner spacers.Type: ApplicationFiled: January 15, 2009Publication date: July 9, 2009Inventor: Cheng-Yao Lo
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Patent number: 7495280Abstract: A MOS device having corner spacers and a method for forming the same are provided. The method includes forming a gate structure overlying a substrate, forming a first dielectric layer over the gate structure and the substrate, forming a second dielectric layer on the first dielectric layer, forming a third dielectric layer on the second dielectric layer, and etching the first, the second and the third dielectric layers using the third dielectric layer as a mask. The remaining first and second dielectric layers have an L-shape. The method further includes implanting source/drain regions, removing remaining portions of the third dielectric layer, blanket forming a fourth dielectric layer, etching the fourth dielectric layer, siliciding exposed source/drain regions, and forming a contact etch stop layer. The remaining portion of the fourth dielectric layer forms corner spacers.Type: GrantFiled: May 16, 2006Date of Patent: February 24, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Cheng-Yao Lo
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Patent number: 7381654Abstract: A method is disclosed for forming right-angle contact/via holes for semiconductor devices. A device is provided on a substrate and covered with a first dielectric layer. A second dielectric layer having an etch rate different from that of the first layer is provided over the first layer. A first photoresist pattern is provided over the second layer to define an X or Y dimension of the contact/via hole. A second photoresist pattern is provided over the second layer to define an opposite dimension of the contact/via hole. First and second pattern dimensions are measured prior to etching to ensure appropriate dimensioning of the etched cavity. A second dry etch is then performed to form the contact/via hole. If the photoresist pattern is not within a desired tolerance, the etching process may be adjusted to ensure the cavity will have the desired dimensions.Type: GrantFiled: May 31, 2005Date of Patent: June 3, 2008Assignee: Taiwan Semiconductor Manufacturing Co.Inventor: Cheng-Yao Lo
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Publication number: 20070267678Abstract: A MOS device having corner spacers and a method for forming the same are provided. The method includes forming a gate structure overlying a substrate, forming a first dielectric layer over the gate structure and the substrate, forming a second dielectric layer on the first dielectric layer, forming a third dielectric layer on the second dielectric layer, and etching the first, the second and the third dielectric layers using the third dielectric layer as a mask. The remaining first and second dielectric layers have an L-shape. The method further includes implanting source/drain regions, removing remaining portions of the third dielectric layer, blanket forming a fourth dielectric layer, etching the fourth dielectric layer, siliciding exposed source/drain regions, and forming a contact etch stop layer. The remaining portion of the fourth dielectric layer forms corner spacers.Type: ApplicationFiled: May 16, 2006Publication date: November 22, 2007Inventor: Cheng-Yao Lo
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Publication number: 20060270068Abstract: A method is disclosed for forming right-angle contact/via holes for semiconductor devices, comprising a two step etching process. A front end device is provided on a substrate and covered with a first dielectric layer. A second dielectric layer having an etch rate different from that of the first layer is provided over the first layer. A first photoresist pattern is provided on the top of the second dielectric layer to define an X or Y dimension of the contact/via hole. A pattern dimension is measured prior to etching to ensure appropriate dimensioning of the etched cavity. A second photoresist pattern is provided on the top of the second dielectric layer to define an opposite dimension of the contact/via hole. A second pattern dimension is measured prior to etching, again to ensure appropriate dimensioning of the etched cavity. A second dry etch is then performed down to the substrate to form the contact/via hole.Type: ApplicationFiled: May 31, 2005Publication date: November 30, 2006Inventor: Cheng-Yao Lo
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Publication number: 20060014351Abstract: A method of forming a low leakage MOS transistor. The transistor includes a gate on a substrate with at least two first spacers adjacent to the gate. A first doped region is formed under each first spacer and a second doped region is formed adjacent to each first doped region, wherein the first doped region and the second doped region are formed in the substrate. A second spacer is formed adjacent to each first spacer. A metal layer is formed on the exposed substrate, the first spacers and the second spacers. The substrate is annealed to form salicide regions on the exposed substrate.Type: ApplicationFiled: July 15, 2004Publication date: January 19, 2006Inventors: Cheng-Yao Lo, Hsien-Chin Lin