Patents by Inventor Cheng-Yeh Hsu
Cheng-Yeh Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230343600Abstract: A method for manufacturing a semiconductor structure and the semiconductor structure are provided. The method for manufacturing a semiconductor structure includes: providing an activated region; forming an initial gate located on the activated region; forming a first mask layer on a top surface of the initial gate, in which a first opening penetrating the first mask layer is provided in the first mask layer, and the first opening at least has opposite two sides extending along a first direction; forming sidewall layers located at least on sidewalls of both sides of the first opening extending in the first direction; removing the first mask layer; patterning the initial gate with the sidewall layers on both sides of the first opening as a mask to form gates.Type: ApplicationFiled: August 2, 2022Publication date: October 26, 2023Inventors: CHENG-YEH HSU, Xiao ZHU, Xiaohong ZHANG
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Publication number: 20220310782Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate, the surface of the semiconductor substrate having a plurality of active areas and shallow trench isolation areas arranged in a first direction; etching the active areas and the shallow trench isolation areas in a direction perpendicular to the first direction to form first recesses and second recesses; covering the surfaces of the first recesses and the second recesses with an adhesive layer and a metal layer; and secondarily etching the metal layer and the adhesive layer in the direction perpendicular to the first direction to form a contact hole, the depth of the adhesive layer in the contact hole being defined as H2.Type: ApplicationFiled: April 12, 2021Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Junchao ZHANG, Cheng Yeh HSU
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Publication number: 20220310618Abstract: The present application relates to the technical field of semiconductor manufacturing, in particular to a method for forming a film layer with uniform thickness distribution and a semiconductor structure. The method for forming a film layer with uniform thickness distribution comprises: providing a substrate, a non-flat surface for forming a film layer being provided in the substrate; forming a first sub-layer on the non-flat surface at a first temperature by an in-situ steam generation process; and, forming a second sub-layer on a surface of the first sub-layer at a second temperature by an in-situ steam generation process, the film layer at least comprising the first sub-layer and the second sub-layer, the second temperature being higher than the first temperature.Type: ApplicationFiled: March 1, 2021Publication date: September 29, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Tao CHEN, Cheng Yeh HSU, WenHao Hsieh
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Publication number: 20220077289Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. The method includes: providing a semiconductor substrate; forming a first wordline trench structure; forming a first sacrificial layer at the bottom of the first wordline trench structure; filling the first wordline trench structure located in active regions by epitaxial growth; forming a first insulation layer covering the top of the semiconductor substrate and the first wordline trench structure; forming a second wordline trench structure and a fin-type structure in the active regions, a depth of the second wordline trench structure being less than that of the first wordline trench structure, and a projection of the second wordline trench structure in a vertical direction completely overlapping with a projection of the first sacrificial layer in the vertical direction; removing the first sacrificial layer; and filling the first wordline trench structure, the second wordline trench structure and the wordline tunnel.Type: ApplicationFiled: November 19, 2021Publication date: March 10, 2022Inventors: Qu Luo, Cheng Yeh Hsu
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Publication number: 20220037481Abstract: Embodiments of the present application provide a semiconductor structure and its fabricating method, and a semiconductor memory. The method of fabricating a semiconductor structure comprises providing a substrate and performing ion implantation on the substrate to form an active area, forming a gate groove on surface of the substrate, measuring depth of the gate groove, and performing ion implantation compensation, if the depth of the gate groove meets a preset condition, on the substrate according to the depth of the gate groove, and forming an ion compensation region in the active area at one side of the gate groove.Type: ApplicationFiled: October 13, 2021Publication date: February 3, 2022Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Bing ZOU, Cheng Yeh HSU
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Patent number: 9401326Abstract: A split contact structure includes a semiconductor substrate having a major surface; a first upwardly protruding structure disposed on the major surface; a first cell contact region in the major surface and being close to the first upwardly protruding structure; a second upwardly protruding structure disposed on the major surface; a second cell contact region in the major surface and being close to the second upwardly protruding structure; a first patterned layer stacked on the first upwardly protruding structure; a second patterned layer stacked on the first upwardly protruding structure; a first contact structure disposed on a sidewall of the first upwardly protruding structure and being in direct contact with the first cell contact region; and a second contact structure disposed on a sidewall of the second upwardly protruding structure and being in direct contact with the second cell contact region.Type: GrantFiled: May 24, 2015Date of Patent: July 26, 2016Assignee: INOTERA MEMORIES, INC.Inventors: Cheng-Yeh Hsu, Hsin-Pin Huang, Chih-Hao Cheng
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Patent number: 8557673Abstract: A manufacturing method of a capacitor structure is provided, which includes the steps of: on a substrate having a first oxide layer, (a) forming a first suspension layer on the first oxide layer; (b) forming a first shallow trench into the first oxide layer above the substrate; (c) forming a second oxide layer filling the first shallow trench; (d) forming a second suspension layer on the second oxide layer; (e) forming a second shallow trench through the second suspension layer into the second oxide layer above the first suspension layer; (f) forming at least one deep trench on the bottom surface of the second shallow trench through the second and the first oxide layers, (g) forming an electrode layer on the inner surface of the deep trench; and (h) removing the first and second oxide layers through the trench openings in the first and the second suspension layers.Type: GrantFiled: May 21, 2012Date of Patent: October 15, 2013Assignee: Inotera Memories, Inc.Inventors: Shin-Bin Huang, Cheng-Yeh Hsu, Chung-Lin Huang
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Publication number: 20130252397Abstract: A manufacturing method of a capacitor structure is provided, which includes the steps of: on a substrate having a first oxide layer, (a) forming a first suspension layer on the first oxide layer; (b) forming a first shallow trench into the first oxide layer above the substrate; (c) forming a second oxide layer filling the first shallow trench; (d) forming a second suspension layer on the second oxide layer; (e) forming a second shallow trench through the second suspension layer into the second oxide layer above the first suspension layer; (f) forming at least one deep trench on the bottom surface of the second shallow trench through the second and the first oxide layers, (g) forming an electrode layer on the inner surface of the deep trench; and (h) removing the first and second oxide layers through the trench openings in the first and the second suspension layers.Type: ApplicationFiled: May 21, 2012Publication date: September 26, 2013Applicant: INOTERA MEMORIES, INC.Inventors: SHIN-BIN HUANG, CHENG-YEH HSU, CHUNG-LIN HUANG
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Patent number: 7829403Abstract: A method for fabricating a semiconductor device is provided. A first active region and a second active region are defined in a substrate. An electrode covering the first active region and the second active region is formed on the substrate. A first sacrificial layer is formed on the second active layer. A first work function electrode is formed on the first active layer by performing a first doping process to a portion of the electrode. The first sacrificial layer is removed. A second sacrificial layer is formed on the first active layer.Type: GrantFiled: June 13, 2008Date of Patent: November 9, 2010Assignee: Inotera Memories, Inc.Inventors: Wen-Hsiang Chen, Cheng-Yeh Hsu
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Publication number: 20090137090Abstract: A method for fabricating a semiconductor device is provided. A first active region and a second active region are defined in a substrate. An electrode covering the first active region and the second active region is formed on the substrate. A first sacrificial layer is formed on the second active layer. A first work function electrode is formed on the first active layer by performing a first doping process to a portion of the electrode. The first sacrificial layer is removed. A second sacrificial layer is formed on the first active layer.Type: ApplicationFiled: June 13, 2008Publication date: May 28, 2009Applicant: INOTERA MEMORIES, INC.Inventors: Wen-Hsiang Chen, Cheng-Yeh Hsu